ASoC: mediatek: mt8183: add audio afe document

Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt b/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt
new file mode 100644 (file)
index 0000000..396ba38
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+++ b/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt
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+Mediatek AFE PCM controller for mt8183
+
+Required properties:
+- compatible = "mediatek,mt68183-audio";
+- reg: register location and size
+- interrupts: should contain AFE interrupt
+- power-domains: should define the power domain
+- clocks: Must contain an entry for each entry in clock-names
+- clock-names: should have these clock names:
+               "infra_sys_audio_clk",
+               "mtkaif_26m_clk",
+               "top_mux_audio",
+               "top_mux_aud_intbus",
+               "top_sys_pll3_d4",
+               "top_clk26m_clk";
+
+Example:
+
+       afe: mt8183-afe-pcm@11220000  {
+               compatible = "mediatek,mt8183-audio";
+               reg = <0 0x11220000 0 0x1000>;
+               interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
+               power-domains = <&scpsys MT8183_POWER_DOMAIN_AUDIO>;
+               clocks = <&infrasys CLK_INFRA_AUDIO>,
+                        <&infrasys CLK_INFRA_AUDIO_26M_BCLK>,
+                        <&topckgen CLK_TOP_MUX_AUDIO>,
+                        <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
+                        <&topckgen CLK_TOP_SYSPLL_D2_D4>,
+                        <&clk26m>;
+               clock-names = "infra_sys_audio_clk",
+                             "mtkaif_26m_clk",
+                             "top_mux_audio",
+                             "top_mux_aud_intbus",
+                             "top_sys_pll_d2_d4",
+                             "top_clk26m_clk";
+       };