]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
drm/amd/display: fix odm output gamma programming
authorDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Fri, 15 Mar 2019 17:59:25 +0000 (13:59 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 28 Mar 2019 03:43:04 +0000 (22:43 -0500)
Currently only top pipe gets output tf programmed. This change
makes all odm head pipes get output tf programmed.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
drivers/gpu/drm/amd/display/dc/inc/resource.h

index caf9d894f95f29d2b8b4fe3618e1ee751a191f7a..d0ed95eda508c79898e8a642ff24e2ea405c5699 100644 (file)
@@ -1302,7 +1302,7 @@ struct pipe_ctx *dc_res_get_odm_bottom_pipe(struct pipe_ctx *pipe_ctx)
        return bottom_pipe;
 }
 
-static bool dc_res_is_odm_bottom_pipe(struct pipe_ctx *pipe_ctx)
+bool dc_res_is_odm_head_pipe(struct pipe_ctx *pipe_ctx)
 {
        struct pipe_ctx *top_pipe = pipe_ctx->top_pipe;
        bool result = false;
@@ -1345,7 +1345,7 @@ bool dc_remove_plane_from_context(
                struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 
                if (pipe_ctx->plane_state == plane_state) {
-                       if (dc_res_is_odm_bottom_pipe(pipe_ctx)) {
+                       if (dc_res_is_odm_head_pipe(pipe_ctx)) {
                                pipe_ctx->plane_state = NULL;
                                pipe_ctx->bottom_pipe = NULL;
                                continue;
index 0a70254d204f8f33bc25490e3a88218fd28217f4..3ce0a4fc58226571d8173f3faa30ef4dd3fe2428 100644 (file)
@@ -172,5 +172,6 @@ void update_audio_usage(
 unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format);
 
 struct pipe_ctx *dc_res_get_odm_bottom_pipe(struct pipe_ctx *pipe_ctx);
+bool dc_res_is_odm_head_pipe(struct pipe_ctx *pipe_ctx);
 
 #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */