ARM: dts: dra7: Add high speed modes capability to MMC1/MMC2 dt node

While the supported UHS mode can be obtained from CAPA2
register, SD Host Controller Standard Specification
doesn't define bits for MMC's HS200 and DDR mode capability.
Add properties to indicate MMC HS200 and DDR speed mode capability in
dt node.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index ae2f8dd46328e8afd5499f8c05279cd540d632cf..9dcd14edc20287f80c73a3b95d21e303ffa6d39c 100644 (file)
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1086,6 +1086,8 @@ mmc1: mmc@4809c000 {
                        status = "disabled";
                        pbias-supply = <&pbias_mmc_reg>;
                        max-frequency = <192000000>;
+                       mmc-ddr-1_8v;
+                       mmc-ddr-3_3v;
                };
 
                hdqw1w: 1w@480b2000 {
@@ -1104,6 +1106,9 @@ mmc2: mmc@480b4000 {
                        max-frequency = <192000000>;
                        /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */
                        sdhci-caps-mask = <0x7 0x0>;
+                       mmc-hs200-1_8v;
+                       mmc-ddr-1_8v;
+                       mmc-ddr-3_3v;
                };
 
                mmc3: mmc@480ad000 {