ARM: dts: exynos: Add CPU perf counters to Exynos54xx boards

Enable support for ARM Performance Monitoring Units available in Cortex-A7
and Cortex-A15 CPU cores for Exynos54xx SoCs (5410, 5420 and 5422/5800).

The PMUs interrupts are defined in the common exynos54xx.dtsi device tree,
but the PMUs are enabled and have their interrupt CPU affinity defined
next to each SoC's cpus node.

Tested with perf on Odroid XU4 (Exynos5422):
armv7_cortex_a7 PMU driver: 5 counters available
armv7_cortex_a15 PMU driver: 7 counters available

Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Marian Mihailescu <mihailescu2m@gmail.com>
Signed-off-by: Willy Wolff <willy.mh.wolff@gmail.com>
[mszyprow: reordered nodes according to krzk request, fixed typos]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 06713ec86f0dad73586e553eb900d284393110ca..c4dbc689e5cb8ebb55b4a36c3618098183cd632f 100644 (file)
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -264,6 +264,11 @@ cpu3_thermal: cpu3-thermal {
        };
 };
 
+&arm_a15_pmu {
+       interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+       status = "okay";
+};
+
 &i2c_0 {
        clocks = <&clock CLK_I2C0>;
        clock-names = "i2c";

diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi
index d7d703aa1699ded9804162b2ed1b089fd625acec..4ee2f9718e8ab257ecdd2174712e5e7c30f7606a 100644 (file)
--- a/arch/arm/boot/dts/exynos5420-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi
@@ -132,3 +132,13 @@ cpu7: cpu@103 {
                };
        };
 };
+
+&arm_a7_pmu {
+       interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
+       status = "okay";
+};
+
+&arm_a15_pmu {
+       interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+       status = "okay";
+};

diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
index ec01d8020c2da99a1096514a93bbaadea14a03af..73fb37d5042d5e599aacc27029629430dd6652ac 100644 (file)
--- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
@@ -131,3 +131,13 @@ cpu7: cpu@3 {
                };
        };
 };
+
+&arm_a7_pmu {
+       interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+       status = "okay";
+};
+
+&arm_a15_pmu {
+       interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
+       status = "okay";
+};

diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi
index b45678212f1aeed9b3a6e85f5a4ff5dbfcc564ca..8f87ab1dd9e3aee2903924e84ddd38a167424df6 100644 (file)
--- a/arch/arm/boot/dts/exynos54xx.dtsi
+++ b/arch/arm/boot/dts/exynos54xx.dtsi
@@ -29,6 +29,26 @@ aliases {
        };
 
        soc: soc {
+               arm_a7_pmu: arm-a7-pmu {
+                       compatible = "arm,cortex-a7-pmu";
+                       interrupt-parent = <&gic>;
+                       interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
+               arm_a15_pmu: arm-a15-pmu {
+                       compatible = "arm,cortex-a15-pmu";
+                       interrupt-parent = <&combiner>;
+                       interrupts = <1 2>,
+                                    <7 0>,
+                                    <16 6>,
+                                    <19 2>;
+                       status = "disabled";
+               };
+
                sysram@2020000 {
                        compatible = "mmio-sram";
                        reg = <0x02020000 0x54000>;