dt-bindings: phy-mtk-tphy: add properties for U2 slew rate calibrate

Add two properties of ref_clk and coefficient used by U2 slew rate
calibrate which may vary on different SoCs

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
index 41e09ed2ca70e2caaf7ee65b2f67651fba7bb9f4..0d34b2b4a6b79600906515679ec45771359d11ac 100644 (file)
--- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
+++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
@@ -27,6 +27,10 @@ Optional properties (controller (parent) node):
  - reg         : offset and length of register shared by multiple ports,
                  exclude port's private register. It is needed on mt2701
                  and mt8173, but not on mt2712.
+ - mediatek,src-ref-clk-mhz    : frequency of reference clock for slew rate
+                 calibrate
+ - mediatek,src-coef   : coefficient for slew rate calibrate, depends on
+                 SoC process
 
 Required properties (port (child) node):
 - reg          : address and length of the register set for the port.