riscv: dts: sifive: Drop "clock-frequency" property of cpu nodes

The "clock-frequency" property of cpu nodes isn't required. Drop it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>

diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index ae5c42d6943a816c363530d43065cdd5d5f3f260..afa43c7ea3690db3fceb535759652a9488d22049 100644 (file)
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -61,7 +61,6 @@ cpu1_intc: interrupt-controller {
                        };
                };
                cpu2: cpu@2 {
-                       clock-frequency = <0>;
                        compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
                        d-cache-block-size = <64>;
                        d-cache-sets = <64>;
@@ -85,7 +84,6 @@ cpu2_intc: interrupt-controller {
                        };
                };
                cpu3: cpu@3 {
-                       clock-frequency = <0>;
                        compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
                        d-cache-block-size = <64>;
                        d-cache-sets = <64>;
@@ -109,7 +107,6 @@ cpu3_intc: interrupt-controller {
                        };
                };
                cpu4: cpu@4 {
-                       clock-frequency = <0>;
                        compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
                        d-cache-block-size = <64>;
                        d-cache-sets = <64>;