drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDI

On Icelake platform, MG PHY is used when operating in DP alternate
mode or the legacy HDMI or DP modes. DDI Ports C, D, E, F are MG PHY
DDI ports on ICL.

This patch adds the necessary voltage swing programming related
register definitions and macros for MG PHY DDI ports.

v4 (from Paulo):
* Use _PORT instead of _PICK
* Change some mask names to our current coding standards
* Stay under 80 columns
v3:
* Rebase on new revision of patches
v2:
* Remove whitespaces in the #defines (Paulo)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180323172419.24911-4-paulo.r.zanoni@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 407ee5ca527f1f7bce6c7b716170843229bb1cab..aa001dd98cc54e5167499cac4b00c9b98f2a3142 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1809,6 +1809,122 @@ enum i915_power_well_id {
 #define   N_SCALAR(x)                  ((x) << 24)
 #define   N_SCALAR_MASK                        (0x7F << 24)
 
+#define _ICL_MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
+       _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
+
+#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1            0x16812C
+#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1            0x16852C
+#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2            0x16912C
+#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT2            0x16952C
+#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT3            0x16A12C
+#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT3            0x16A52C
+#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT4            0x16B12C
+#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT4            0x16B52C
+#define ICL_PORT_MG_TX1_LINK_PARAMS(port, ln) \
+       _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
+                                     _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
+                                     _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1)
+
+#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1            0x1680AC
+#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1            0x1684AC
+#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2            0x1690AC
+#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT2            0x1694AC
+#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT3            0x16A0AC
+#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT3            0x16A4AC
+#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT4            0x16B0AC
+#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT4            0x16B4AC
+#define ICL_PORT_MG_TX2_LINK_PARAMS(port, ln) \
+       _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
+                                     _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
+                                     _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1)
+#define CRI_USE_FS32                   (1 << 5)
+
+#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1          0x16814C
+#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1          0x16854C
+#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2          0x16914C
+#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT2          0x16954C
+#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT3          0x16A14C
+#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT3          0x16A54C
+#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT4          0x16B14C
+#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT4          0x16B54C
+#define ICL_PORT_MG_TX1_PISO_READLOAD(port, ln) \
+       _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
+                                     _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
+                                     _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1)
+
+#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1          0x1680CC
+#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1          0x1684CC
+#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2          0x1690CC
+#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT2          0x1694CC
+#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT3          0x16A0CC
+#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT3          0x16A4CC
+#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT4          0x16B0CC
+#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT4          0x16B4CC
+#define ICL_PORT_MG_TX2_PISO_READLOAD(port, ln) \
+       _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
+                                     _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
+                                     _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1)
+#define CRI_CALCINIT                                   (1 << 1)
+
+#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1              0x168148
+#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1              0x168548
+#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2              0x169148
+#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT2              0x169548
+#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT3              0x16A148
+#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT3              0x16A548
+#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT4              0x16B148
+#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT4              0x16B548
+#define ICL_PORT_MG_TX1_SWINGCTRL(port, ln) \
+       _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1, \
+                                     _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2, \
+                                     _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1)
+
+#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1              0x1680C8
+#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1              0x1684C8
+#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2              0x1690C8
+#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT2              0x1694C8
+#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT3              0x16A0C8
+#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT3              0x16A4C8
+#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT4              0x16B0C8
+#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT4              0x16B4C8
+#define ICL_PORT_MG_TX2_SWINGCTRL(port, ln) \
+       _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1, \
+                                     _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2, \
+                                     _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1)
+#define CRI_TXDEEMPH_OVERRIDE_17_12(x)                 ((x) << 0)
+#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK               (0x3F << 0)
+
+#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1                        0x168144
+#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1                        0x168544
+#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2                        0x169144
+#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT2                        0x169544
+#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT3                        0x16A144
+#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT3                        0x16A544
+#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT4                        0x16B144
+#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT4                        0x16B544
+#define ICL_PORT_MG_TX1_DRVCTRL(port, ln) \
+       _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1, \
+                                     _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2, \
+                                     _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1)
+
+#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1                        0x1680C4
+#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1                        0x1684C4
+#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2                        0x1690C4
+#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT2                        0x1694C4
+#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT3                        0x16A0C4
+#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT3                        0x16A4C4
+#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT4                        0x16B0C4
+#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT4                        0x16B4C4
+#define ICL_PORT_MG_TX2_DRVCTRL(port, ln) \
+       _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1, \
+                                     _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2, \
+                                     _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1)
+#define CRI_TXDEEMPH_OVERRIDE_11_6(x)                  ((x) << 24)
+#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK                        (0x3F << 24)
+#define CRI_TXDEEMPH_OVERRIDE_EN                       (1 << 22)
+#define CRI_TXDEEMPH_OVERRIDE_5_0(x)                   ((x) << 16)
+#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK                 (0x3F << 16)
+
 /* The spec defines this only for BXT PHY0, but lets assume that this
  * would exist for PHY1 too if it had a second channel.
  */