soc: mediatek: add SCPSYS power domain driver for MediaTek MT7623A SoC

Add SCPSYS power domain driver for MT7623A SoC. The MT7623A's power
domains are the subset of MT7623 SoC's ones. As MT7623 SoC has full
features whereas MT7623A is being designed just for router applications.
Thus, MT7623A doesn't include those power domains multimedia function
belongs to. In order to avoid certain errors undoubtedly happening at
registering those power domains on MT7623A SoC using the existing MT7623
SCPSYS driver, it's required to define another setup specifically for
MT7623A SoC.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 5346f33dd70b612eac93b385ab07fb8a954f702c..fc55faa178673a8b144d9d5c3536af97cd8d5160 100644 (file)
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -24,6 +24,7 @@
 #include <dt-bindings/power/mt2712-power.h>
 #include <dt-bindings/power/mt6797-power.h>
 #include <dt-bindings/power/mt7622-power.h>
+#include <dt-bindings/power/mt7623a-power.h>
 #include <dt-bindings/power/mt8173-power.h>
 
 #define SPM_VDE_PWR_CON                        0x0210
@@ -794,6 +795,47 @@ static const struct scp_domain_data scp_domain_data_mt7622[] = {
        },
 };
 
+/*
+ * MT7623A power domain support
+ */
+
+static const struct scp_domain_data scp_domain_data_mt7623a[] = {
+       [MT7623A_POWER_DOMAIN_CONN] = {
+               .name = "conn",
+               .sta_mask = PWR_STATUS_CONN,
+               .ctl_offs = SPM_CONN_PWR_CON,
+               .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
+                                MT2701_TOP_AXI_PROT_EN_CONN_S,
+               .clk_id = {CLK_NONE},
+               .active_wakeup = true,
+       },
+       [MT7623A_POWER_DOMAIN_ETH] = {
+               .name = "eth",
+               .sta_mask = PWR_STATUS_ETH,
+               .ctl_offs = SPM_ETH_PWR_CON,
+               .sram_pdn_bits = GENMASK(11, 8),
+               .sram_pdn_ack_bits = GENMASK(15, 12),
+               .clk_id = {CLK_ETHIF},
+               .active_wakeup = true,
+       },
+       [MT7623A_POWER_DOMAIN_HIF] = {
+               .name = "hif",
+               .sta_mask = PWR_STATUS_HIF,
+               .ctl_offs = SPM_HIF_PWR_CON,
+               .sram_pdn_bits = GENMASK(11, 8),
+               .sram_pdn_ack_bits = GENMASK(15, 12),
+               .clk_id = {CLK_ETHIF},
+               .active_wakeup = true,
+       },
+       [MT7623A_POWER_DOMAIN_IFR_MSC] = {
+               .name = "ifr_msc",
+               .sta_mask = PWR_STATUS_IFR_MSC,
+               .ctl_offs = SPM_IFR_MSC_PWR_CON,
+               .clk_id = {CLK_NONE},
+               .active_wakeup = true,
+       },
+};
+
 /*
  * MT8173 power domain support
  */
@@ -935,6 +977,16 @@ static const struct scp_soc_data mt7622_data = {
        .bus_prot_reg_update = true,
 };
 
+static const struct scp_soc_data mt7623a_data = {
+       .domains = scp_domain_data_mt7623a,
+       .num_domains = ARRAY_SIZE(scp_domain_data_mt7623a),
+       .regs = {
+               .pwr_sta_offs = SPM_PWR_STATUS,
+               .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
+       },
+       .bus_prot_reg_update = true,
+};
+
 static const struct scp_soc_data mt8173_data = {
        .domains = scp_domain_data_mt8173,
        .num_domains = ARRAY_SIZE(scp_domain_data_mt8173),
@@ -964,6 +1016,9 @@ static const struct of_device_id of_scpsys_match_tbl[] = {
        }, {
                .compatible = "mediatek,mt7622-scpsys",
                .data = &mt7622_data,
+       }, {
+               .compatible = "mediatek,mt7623a-scpsys",
+               .data = &mt7623a_data,
        }, {
                .compatible = "mediatek,mt8173-scpsys",
                .data = &mt8173_data,