Merge remote-tracking branches 'spi/topic/sun4i', 'spi/topic/topcliff-pch' and 'spi...

diff --combined drivers/spi/Kconfig
index 0876d595379774a78f8880d55c0358e8850bd4c6,8b9c2a38d1ccd8ae00d9f2642026438d349c8be1,7c78d52591af69591cedf842f2222023b8713d89,8b9c2a38d1ccd8ae00d9f2642026438d349c8be1..77064160dd762c26f6c1fd184b252b24360163e3
--- 1/drivers/spi/Kconfig
--- 2/drivers/spi/Kconfig
--- 3/drivers/spi/Kconfig
--- 4/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@@@@ -585,7 -585,7 -585,7 -585,7 +585,7 @@@@@ config SPI_TEGRA20_SLIN
    
    config SPI_TOPCLIFF_PCH
        tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) SPI"
-- -    depends on PCI && (X86_32 || COMPILE_TEST)
++ +    depends on PCI && (X86_32 || MIPS || COMPILE_TEST)
        help
          SPI driver for the Topcliff PCH (Platform Controller Hub) SPI bus
          used in some x86 embedded processors.
@@@@@ -689,15 -689,6 -689,6 -689,6 +689,15 @@@@@ config SPI_SPIDE
          Note that this application programming interface is EXPERIMENTAL
          and hence SUBJECT TO CHANGE WITHOUT NOTICE while it stabilizes.
    
 +++config SPI_LOOPBACK_TEST
 +++    tristate "spi loopback test framework support"
 +++    depends on m
 +++    help
 +++      This enables the SPI loopback testing framework driver
 +++
 +++      primarily used for development of spi_master drivers
 +++      and to detect regressions
 +++
    config SPI_TLE62X0
        tristate "Infineon TLE62X0 (for power switching)"
        depends on SYSFS

diff --combined drivers/spi/spi-sun4i.c
index a6d936c68674ce20216d28b20022995990075761,f60a6d634d61a68588fde88aeb9b37cee9bd9ac8,fbb0a4d74e91c6716d6adc87c8c9bbae91487ed5,fbb0a4d74e91c6716d6adc87c8c9bbae91487ed5..1ddd9e2309b685576a8c63abc1770f731a7acd0c
--- 1/drivers/spi/spi-sun4i.c
--- 2/drivers/spi/spi-sun4i.c
--- 3/drivers/spi/spi-sun4i.c
--- 4/drivers/spi/spi-sun4i.c
+++ b/drivers/spi/spi-sun4i.c
@@@@@ -140,9 -140,6 -140,6 -140,6 +140,9 @@@@@ static void sun4i_spi_set_cs(struct spi
        reg &= ~SUN4I_CTL_CS_MASK;
        reg |= SUN4I_CTL_CS(spi->chip_select);
    
 +++    /* We want to control the chip select manually */
 +++    reg |= SUN4I_CTL_CS_MANUAL;
 +++
        if (enable)
                reg |= SUN4I_CTL_CS_LEVEL;
        else
@@@@@ -225,12 -222,15 -222,15 -222,15 +225,12 @@@@@ static int sun4i_spi_transfer_one(struc
        else
                reg |= SUN4I_CTL_DHB;
    
 ---    /* We want to control the chip select manually */
 ---    reg |= SUN4I_CTL_CS_MANUAL;
 ---
        sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
    
        /* Ensure that we have a parent clock fast enough */
        mclk_rate = clk_get_rate(sspi->mclk);
- --    if (mclk_rate < (2 * spi->max_speed_hz)) {
- --            clk_set_rate(sspi->mclk, 2 * spi->max_speed_hz);
+ ++    if (mclk_rate < (2 * tfr->speed_hz)) {
+ ++            clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
                mclk_rate = clk_get_rate(sspi->mclk);
        }
    
@@@@@ -248,14 -248,14 -248,14 -248,14 +248,14 @@@@@
         * First try CDR2, and if we can't reach the expected
         * frequency, fall back to CDR1.
         */
- --    div = mclk_rate / (2 * spi->max_speed_hz);
+ ++    div = mclk_rate / (2 * tfr->speed_hz);
        if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
                if (div > 0)
                        div--;
    
                reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
        } else {
- --            div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz);
+ ++            div = ilog2(mclk_rate) - ilog2(tfr->speed_hz);
                reg = SUN4I_CLK_CTL_CDR1(div);
        }