RDMA/hns: Add vlan enable bit for hip08

In order to extend vlan device range, the design add two field of qp
context for checking vlan packet in sender and in recevicer.

Signed-off-by: Lijun Ou <oulijun@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>

diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
index 4b8266d7ade16b6c7dd0b587205aa9c96b2abddc..f2bf9b5c5faf83225d79ea208df0876886ea8b41 100644 (file)
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
@@ -3608,6 +3608,17 @@ static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
                        memcpy(src_mac, gid_attr->ndev->dev_addr, ETH_ALEN);
                }
 
+               if (is_vlan_dev(gid_attr->ndev)) {
+                       roce_set_bit(context->byte_76_srqn_op_en,
+                                    V2_QPC_BYTE_76_RQ_VLAN_EN_S, 1);
+                       roce_set_bit(qpc_mask->byte_76_srqn_op_en,
+                                    V2_QPC_BYTE_76_RQ_VLAN_EN_S, 0);
+                       roce_set_bit(context->byte_168_irrl_idx,
+                                    V2_QPC_BYTE_168_SQ_VLAN_EN_S, 1);
+                       roce_set_bit(qpc_mask->byte_168_irrl_idx,
+                                    V2_QPC_BYTE_168_SQ_VLAN_EN_S, 0);
+               }
+
                roce_set_field(context->byte_24_mtu_tc,
                               V2_QPC_BYTE_24_VLAN_ID_M,
                               V2_QPC_BYTE_24_VLAN_ID_S, vlan);

diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
index c399ac36afa12c1aa967ab3011ddb2eb1108b98b..f8abccea152cf793578a98cad66b6280715e0452 100644 (file)
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
@@ -527,6 +527,7 @@ struct hns_roce_v2_qp_context {
 
 #define        V2_QPC_BYTE_76_RQIE_S 28
 
+#define        V2_QPC_BYTE_76_RQ_VLAN_EN_S 30
 #define        V2_QPC_BYTE_80_RX_CQN_S 0
 #define V2_QPC_BYTE_80_RX_CQN_M GENMASK(23, 0)
 
@@ -628,6 +629,7 @@ struct hns_roce_v2_qp_context {
 #define        V2_QPC_BYTE_168_LP_SGEN_INI_S 22
 #define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 22)
 
+#define V2_QPC_BYTE_168_SQ_VLAN_EN_S 24
 #define V2_QPC_BYTE_168_POLL_DB_WAIT_DO_S 25
 #define V2_QPC_BYTE_168_SCC_TOKEN_FORBID_SQ_DEQ_S 26
 #define V2_QPC_BYTE_168_WAIT_ACK_TIMEOUT_S 27