[media] marvell-ccic: fix RGB444 format

The RGB444 format swapped the red and blue components, fix this.

Rather than making a new BGR444 format (as I proposed initially), Jon prefers
to just fix this and return the colors in the right order. I think that makes
sense in this case.

Since the RGB444 pixel format is deprecated due to the ambiguous specification
of the alpha component we use the XRGB444 pixel format instead (specified as having
no alpha channel).

Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Acked-by: Jonathan Corbet <corbet@lwn.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>

diff --git a/drivers/media/platform/marvell-ccic/mcam-core.c b/drivers/media/platform/marvell-ccic/mcam-core.c
index ce5b0eaf0c2098e9482ce4dea22e2d1eaa6b0244..5e2b4df48b3c93ee7ce89c4bcb08cc2000660358 100644 (file)
--- a/drivers/media/platform/marvell-ccic/mcam-core.c
+++ b/drivers/media/platform/marvell-ccic/mcam-core.c
@@ -138,8 +138,8 @@ static struct mcam_format_struct {
                .planar         = true,
        },
        {
-               .desc           = "RGB 444",
-               .pixelformat    = V4L2_PIX_FMT_RGB444,
+               .desc           = "XRGB 444",
+               .pixelformat    = V4L2_PIX_FMT_XRGB444,
                .mbus_code      = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE,
                .bpp            = 2,
                .planar         = false,
@@ -777,10 +777,9 @@ static void mcam_ctlr_image(struct mcam_camera *cam)
                mcam_reg_write_mask(cam, REG_CTRL0,
                        C0_DF_YUV | C0_YUV_PACKED | C0_YUVE_SWAP24, C0_DF_MASK);
                break;
-       case V4L2_PIX_FMT_RGB444:
+       case V4L2_PIX_FMT_XRGB444:
                mcam_reg_write_mask(cam, REG_CTRL0,
-                       C0_DF_RGB | C0_RGBF_444 | C0_RGB4_XRGB, C0_DF_MASK);
-               /* Alpha value? */
+                       C0_DF_RGB | C0_RGBF_444 | C0_RGB4_XBGR, C0_DF_MASK);
                break;
        case V4L2_PIX_FMT_RGB565:
                mcam_reg_write_mask(cam, REG_CTRL0,