]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
pinctrl: sunxi: Disable strict mode for old pinctrl drivers
authorMaxime Ripard <maxime.ripard@free-electrons.com>
Mon, 9 Oct 2017 20:53:38 +0000 (22:53 +0200)
committerLinus Walleij <linus.walleij@linaro.org>
Tue, 31 Oct 2017 08:45:00 +0000 (09:45 +0100)
Old pinctrl drivers will need to disable strict mode for various reasons,
among which:
  - Some DT will still have a pinctrl group for each GPIO used, which will
    be rejected by pin_request. While we could remove those nodes, we still
    have to deal with old DTs.
  - Some GPIOs on these boards need to have their pin configuration changed
    (for bias or current), and there's no clear migration path

Let's disable the strict mode on those SoCs so that there's no breakage.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
drivers/pinctrl/sunxi/pinctrl-sun5i.c
drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c
drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c
drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c
drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c
drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c

index f763d8d62d6ea94b2de965242d08c23c1be30a1c..295e48fc94bc087923340792ffefdd04172e404a 100644 (file)
@@ -1289,6 +1289,7 @@ static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
        .npins = ARRAY_SIZE(sun4i_a10_pins),
        .irq_banks = 1,
        .irq_read_needs_mux = true,
+       .disable_strict_mode = true,
 };
 
 static int sun4i_a10_pinctrl_probe(struct platform_device *pdev)
index 47afd558b11484e6ef5dc90932b4c39d2ac017f9..27ec99e81c4c310dacc01d8eb786f6a36a3247f4 100644 (file)
@@ -713,6 +713,7 @@ static const struct sunxi_pinctrl_desc sun5i_pinctrl_data = {
        .pins = sun5i_pins,
        .npins = ARRAY_SIZE(sun5i_pins),
        .irq_banks = 1,
+       .disable_strict_mode = true,
 };
 
 static int sun5i_pinctrl_probe(struct platform_device *pdev)
index 49a1deb97bb75912c77c37f5bc1fed19b1244cfc..a00246d3dd49700de4eb81ef14843f10629a5604 100644 (file)
@@ -106,6 +106,7 @@ static const struct sunxi_pinctrl_desc sun6i_a31_r_pinctrl_data = {
        .npins = ARRAY_SIZE(sun6i_a31_r_pins),
        .pin_base = PL_BASE,
        .irq_banks = 2,
+       .disable_strict_mode = true,
 };
 
 static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev)
index 951a25c1881564e1644ba57bd4df700a743a9ed3..82ffaf4668923347b8e6a04430dc1017e8c93ba6 100644 (file)
@@ -965,6 +965,7 @@ static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = {
        .pins = sun6i_a31_pins,
        .npins = ARRAY_SIZE(sun6i_a31_pins),
        .irq_banks = 4,
+       .disable_strict_mode = true,
 };
 
 static int sun6i_a31_pinctrl_probe(struct platform_device *pdev)
index 67ee6f9b3b68981508748d351fe5cebffad94ccc..8a08c4afc6a8686dff0ed5c21b2bce0fe293b226 100644 (file)
@@ -93,6 +93,7 @@ static const struct sunxi_pinctrl_desc sun8i_a23_r_pinctrl_data = {
        .npins = ARRAY_SIZE(sun8i_a23_r_pins),
        .pin_base = PL_BASE,
        .irq_banks = 1,
+       .disable_strict_mode = true,
 };
 
 static int sun8i_a23_r_pinctrl_probe(struct platform_device *pdev)
index 721b6935baf308820f74705e1de7a4ba8f889f1e..402fd7d21e7b63b216ab02f0e075dff51492d609 100644 (file)
@@ -563,6 +563,7 @@ static const struct sunxi_pinctrl_desc sun8i_a23_pinctrl_data = {
        .pins = sun8i_a23_pins,
        .npins = ARRAY_SIZE(sun8i_a23_pins),
        .irq_banks = 3,
+       .disable_strict_mode = true,
 };
 
 static int sun8i_a23_pinctrl_probe(struct platform_device *pdev)
index ef1e0bef4099f95c2651a8bdce6803d0cea13235..da387211a75e8d21e596d20abe6ee3e0bd4c011f 100644 (file)
@@ -486,6 +486,7 @@ static const struct sunxi_pinctrl_desc sun8i_a33_pinctrl_data = {
        .npins = ARRAY_SIZE(sun8i_a33_pins),
        .irq_banks = 2,
        .irq_bank_base = 1,
+       .disable_strict_mode = true,
 };
 
 static int sun8i_a33_pinctrl_probe(struct platform_device *pdev)
index ebfd9a26628c93cb5b70aadc0b8111b0f69e2ec0..b795a199e240420a345467bbe7e0a3b8b9eb6e07 100644 (file)
@@ -82,7 +82,8 @@ static const struct sunxi_pinctrl_desc sun8i_h3_r_pinctrl_data = {
        .npins = ARRAY_SIZE(sun8i_h3_r_pins),
        .irq_banks = 1,
        .pin_base = PL_BASE,
-       .irq_read_needs_mux = true
+       .irq_read_needs_mux = true,
+       .disable_strict_mode = true,
 };
 
 static int sun8i_h3_r_pinctrl_probe(struct platform_device *pdev)
index 518a92df441874c347687cbe946073a0b79f6823..d1719a738c207d5ced37a5cd80255ad96ac067c2 100644 (file)
@@ -491,7 +491,8 @@ static const struct sunxi_pinctrl_desc sun8i_h3_pinctrl_data = {
        .pins = sun8i_h3_pins,
        .npins = ARRAY_SIZE(sun8i_h3_pins),
        .irq_banks = 2,
-       .irq_read_needs_mux = true
+       .irq_read_needs_mux = true,
+       .disable_strict_mode = true,
 };
 
 static int sun8i_h3_pinctrl_probe(struct platform_device *pdev)
index 92a873f736975c2d96cefc8bb135b40b79f22d37..c63086c9833575e3535f5c63678dfbd94857c7ac 100644 (file)
@@ -152,6 +152,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_r_pinctrl_data = {
        .npins = ARRAY_SIZE(sun9i_a80_r_pins),
        .pin_base = PL_BASE,
        .irq_banks = 2,
+       .disable_strict_mode = true,
 };
 
 static int sun9i_a80_r_pinctrl_probe(struct platform_device *pdev)
index bc14e954d7a2abd923add205a57cb850e72fb65d..472ef0d91b9929c4628084a020374b68d3de3c86 100644 (file)
@@ -721,6 +721,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_pinctrl_data = {
        .pins = sun9i_a80_pins,
        .npins = ARRAY_SIZE(sun9i_a80_pins),
        .irq_banks = 5,
+       .disable_strict_mode = true,
 };
 
 static int sun9i_a80_pinctrl_probe(struct platform_device *pdev)