]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
arm64: dts: rockchip: Enable SPI NOR flash on Rock64
authorChen-Yu Tsai <wens@csie.org>
Wed, 26 Sep 2018 04:53:57 +0000 (12:53 +0800)
committerHeiko Stuebner <heiko@sntech.de>
Wed, 26 Sep 2018 11:37:52 +0000 (13:37 +0200)
The Pine64 Rock64 board comes with a GigaDevice GD25Q128CSIG
or GD25Q127CSIG chip, which is a 128 Mbit SPI NOR flash chip
that supports the JEDEC read-ID command.

This patch enables the SPI controller and adds a device node
for the flash chip using the generic "jedec,spi-nor" comaptible.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm64/boot/dts/rockchip/rk3328-rock64.dts

index 9ee4f57557f3f6bb04c5c5c67168b156d69ba661..2170cf63845ed93d198ecc380cabb7e6362a57c0 100644 (file)
@@ -290,6 +290,18 @@ spdif_p0_0: endpoint {
        };
 };
 
+&spi0 {
+       status = "okay";
+
+       spiflash@0 {
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+
+               /* maximum speed for Rockchip SPI */
+               spi-max-frequency = <50000000>;
+       };
+};
+
 &tsadc {
        rockchip,hw-tshut-mode = <0>;
        rockchip,hw-tshut-polarity = <0>;