drm/i915/icl: Apply a recommended rc6 threshold

On gen11 the recommended rc6 threshold differs from previous
gens, apply it. Move the write to a correct spot in sequence.

v2: do write in 2b, fix bspec ref (Michal)

Bspec: 33149
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190410105923.18546-2-mika.kuoppala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4d87790aefa119b93dfc1212a9b5ce74680c9034..b7946a73cea39d199ccf0e8519e97a8c3c8103a8 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7151,6 +7151,8 @@ static void gen11_enable_rc6(struct drm_i915_private *dev_priv)
 
        I915_WRITE(GEN6_RC_SLEEP, 0);
 
+       I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
+
        /*
         * 2c: Program Coarse Power Gating Policies.
         *
@@ -7176,8 +7178,6 @@ static void gen11_enable_rc6(struct drm_i915_private *dev_priv)
        I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
 
        /* 3a: Enable RC6 */
-       I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
-
        I915_WRITE(GEN6_RC_CONTROL,
                   GEN6_RC_CTL_HW_ENABLE |
                   GEN6_RC_CTL_RC6_ENABLE |