drm/amd/pp: Change pstate_clk frequency unit to 10KHz on Rv

to keep consistent with other asics

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 7712eb62539a75ddfd40d1df904799cecdd7d549..ef09073c88d95abc278534caf301b364715a4039 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -479,8 +479,8 @@ static int smu10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 
        hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
 
-       hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK;
-       hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK;
+       hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK * 100;
+       hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK * 100;
 
        return result;
 }