RISC-V: SMP cleanup and new features

This patch series now has evolved to contain several related changes.

1. Updated the assorted cleanup series by Palmer.
The original cleanup patch series can be found here.
http://lists.infradead.org/pipermail/linux-riscv/2018-August/001232.html

2. Implemented decoupling linux logical CPU ids from hart id.
Some of the work has been inspired from ARM64.
Tested on QEMU & HighFive Unleashed board with/without SMP enabled.

3. Included Anup's cleanup and IPI stat patch.

All the patch series have been combined to avoid conflicts as a lot of
common code is changed different patch sets. Atish has mostly addressed
review comments and fixed checkpatch errors from Palmer's and Anup's
series.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

diff --combined arch/riscv/kernel/entry.S
index 59c02e2bf739dcff80f2d0e94e7837a69a965fd9,6eaacfa5b63d6d57b0cd354b74098647c9e34d01..13d4826ab2a1d3610504bbf30ff6625507244ad2
--- 1/arch/riscv/kernel/entry.S
--- 2/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@@ -168,7 -168,6 +168,6 @@@ ENTRY(handle_exception
  
        /* Handle interrupts */
        move a0, sp /* pt_regs */
-       move a1, s4 /* scause */
        tail do_IRQ
  1:
        /* Exceptions run with interrupts enabled */
@@@ -357,6 -356,93 +356,6 @@@ ENTRY(__switch_to
        ret
  ENDPROC(__switch_to)
  
 -ENTRY(__fstate_save)
 -      li  a2,  TASK_THREAD_F0
 -      add a0, a0, a2
 -      li t1, SR_FS
 -      csrs sstatus, t1
 -      frcsr t0
 -      fsd f0,  TASK_THREAD_F0_F0(a0)
 -      fsd f1,  TASK_THREAD_F1_F0(a0)
 -      fsd f2,  TASK_THREAD_F2_F0(a0)
 -      fsd f3,  TASK_THREAD_F3_F0(a0)
 -      fsd f4,  TASK_THREAD_F4_F0(a0)
 -      fsd f5,  TASK_THREAD_F5_F0(a0)
 -      fsd f6,  TASK_THREAD_F6_F0(a0)
 -      fsd f7,  TASK_THREAD_F7_F0(a0)
 -      fsd f8,  TASK_THREAD_F8_F0(a0)
 -      fsd f9,  TASK_THREAD_F9_F0(a0)
 -      fsd f10, TASK_THREAD_F10_F0(a0)
 -      fsd f11, TASK_THREAD_F11_F0(a0)
 -      fsd f12, TASK_THREAD_F12_F0(a0)
 -      fsd f13, TASK_THREAD_F13_F0(a0)
 -      fsd f14, TASK_THREAD_F14_F0(a0)
 -      fsd f15, TASK_THREAD_F15_F0(a0)
 -      fsd f16, TASK_THREAD_F16_F0(a0)
 -      fsd f17, TASK_THREAD_F17_F0(a0)
 -      fsd f18, TASK_THREAD_F18_F0(a0)
 -      fsd f19, TASK_THREAD_F19_F0(a0)
 -      fsd f20, TASK_THREAD_F20_F0(a0)
 -      fsd f21, TASK_THREAD_F21_F0(a0)
 -      fsd f22, TASK_THREAD_F22_F0(a0)
 -      fsd f23, TASK_THREAD_F23_F0(a0)
 -      fsd f24, TASK_THREAD_F24_F0(a0)
 -      fsd f25, TASK_THREAD_F25_F0(a0)
 -      fsd f26, TASK_THREAD_F26_F0(a0)
 -      fsd f27, TASK_THREAD_F27_F0(a0)
 -      fsd f28, TASK_THREAD_F28_F0(a0)
 -      fsd f29, TASK_THREAD_F29_F0(a0)
 -      fsd f30, TASK_THREAD_F30_F0(a0)
 -      fsd f31, TASK_THREAD_F31_F0(a0)
 -      sw t0, TASK_THREAD_FCSR_F0(a0)
 -      csrc sstatus, t1
 -      ret
 -ENDPROC(__fstate_save)
 -
 -ENTRY(__fstate_restore)
 -      li  a2,  TASK_THREAD_F0
 -      add a0, a0, a2
 -      li t1, SR_FS
 -      lw t0, TASK_THREAD_FCSR_F0(a0)
 -      csrs sstatus, t1
 -      fld f0,  TASK_THREAD_F0_F0(a0)
 -      fld f1,  TASK_THREAD_F1_F0(a0)
 -      fld f2,  TASK_THREAD_F2_F0(a0)
 -      fld f3,  TASK_THREAD_F3_F0(a0)
 -      fld f4,  TASK_THREAD_F4_F0(a0)
 -      fld f5,  TASK_THREAD_F5_F0(a0)
 -      fld f6,  TASK_THREAD_F6_F0(a0)
 -      fld f7,  TASK_THREAD_F7_F0(a0)
 -      fld f8,  TASK_THREAD_F8_F0(a0)
 -      fld f9,  TASK_THREAD_F9_F0(a0)
 -      fld f10, TASK_THREAD_F10_F0(a0)
 -      fld f11, TASK_THREAD_F11_F0(a0)
 -      fld f12, TASK_THREAD_F12_F0(a0)
 -      fld f13, TASK_THREAD_F13_F0(a0)
 -      fld f14, TASK_THREAD_F14_F0(a0)
 -      fld f15, TASK_THREAD_F15_F0(a0)
 -      fld f16, TASK_THREAD_F16_F0(a0)
 -      fld f17, TASK_THREAD_F17_F0(a0)
 -      fld f18, TASK_THREAD_F18_F0(a0)
 -      fld f19, TASK_THREAD_F19_F0(a0)
 -      fld f20, TASK_THREAD_F20_F0(a0)
 -      fld f21, TASK_THREAD_F21_F0(a0)
 -      fld f22, TASK_THREAD_F22_F0(a0)
 -      fld f23, TASK_THREAD_F23_F0(a0)
 -      fld f24, TASK_THREAD_F24_F0(a0)
 -      fld f25, TASK_THREAD_F25_F0(a0)
 -      fld f26, TASK_THREAD_F26_F0(a0)
 -      fld f27, TASK_THREAD_F27_F0(a0)
 -      fld f28, TASK_THREAD_F28_F0(a0)
 -      fld f29, TASK_THREAD_F29_F0(a0)
 -      fld f30, TASK_THREAD_F30_F0(a0)
 -      fld f31, TASK_THREAD_F31_F0(a0)
 -      fscsr t0
 -      csrc sstatus, t1
 -      ret
 -ENDPROC(__fstate_restore)
 -
 -
        .section ".rodata"
        /* Exception vector table */
  ENTRY(excp_vect_table)

diff --combined arch/riscv/kernel/setup.c
index c9461985db7e753bb67da682453ca72163e6b3ed,5e9e6f934cc036af2263bd9444ebed1a62a66139..2c290e6aaa6e414a965d7acc97604a26f75e7548
--- 1/arch/riscv/kernel/setup.c
--- 2/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@@ -81,6 -81,16 +81,16 @@@ EXPORT_SYMBOL(empty_zero_page)
  
  /* The lucky hart to first increment this variable will boot the other cores */
  atomic_t hart_lottery;
+ unsigned long boot_cpu_hartid;
+ 
+ unsigned long __cpuid_to_hartid_map[NR_CPUS] = {
+       [0 ... NR_CPUS-1] = INVALID_HARTID
+ };
+ 
+ void __init smp_setup_processor_id(void)
+ {
+       cpuid_to_hartid_map(0) = boot_cpu_hartid;
+ }
  
  #ifdef CONFIG_BLK_DEV_INITRD
  static void __init setup_initrd(void)
@@@ -227,10 -237,7 +237,10 @@@ void __init setup_arch(char **cmdline_p
        setup_bootmem();
        paging_init();
        unflatten_device_tree();
 +
 +#ifdef CONFIG_SWIOTLB
        swiotlb_init(1);
 +#endif
  
  #ifdef CONFIG_SMP
        setup_smp();