dt-bindings: spi: Add device tree binding documentation for Zynq QSPI controller

This patch adds the dts binding document for Zynq SOC QSPI controller.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
new file mode 100644 (file)
index 0000000..16b734a
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
@@ -0,0 +1,25 @@
+Xilinx Zynq QSPI controller Device Tree Bindings
+-------------------------------------------------------------------
+
+Required properties:
+- compatible           : Should be "xlnx,zynq-qspi-1.0".
+- reg                  : Physical base address and size of QSPI registers map.
+- interrupts           : Property with a value describing the interrupt
+                         number.
+- clock-names          : List of input clock names - "ref_clk", "pclk"
+                         (See clock bindings for details).
+- clocks               : Clock phandles (see clock bindings for details).
+
+Optional properties:
+- num-cs               : Number of chip selects used.
+
+Example:
+       qspi: spi@e000d000 {
+               compatible = "xlnx,zynq-qspi-1.0";
+               reg = <0xe000d000 0x1000>;
+               interrupt-parent = <&intc>;
+               interrupts = <0 19 4>;
+               clock-names = "ref_clk", "pclk";
+               clocks = <&clkc 10>, <&clkc 43>;
+               num-cs = <1>;
+       };