drm/amd/display: update sr and pstate latencies for Renoir

[Why]
DF team has produced more optimized latency numbers.

[How]
Add sr latencies to the wm table, use different latencies
for different wm sets.
Also fix bb override from registery key for these latencies.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 790a2d211bd6db21a6a04cccd4c7bc9cad0f4a60..841095d09d3c2137e6dc80470c9895c0eb8e34a1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -523,25 +523,33 @@ struct clk_bw_params rn_bw_params = {
                        {
                                .wm_inst = WM_A,
                                .wm_type = WM_TYPE_PSTATE_CHG,
-                               .pstate_latency_us = 23.84,
+                               .pstate_latency_us = 11.72,
+                               .sr_exit_time_us = 6.09,
+                               .sr_enter_plus_exit_time_us = 7.14,
                                .valid = true,
                        },
                        {
                                .wm_inst = WM_B,
                                .wm_type = WM_TYPE_PSTATE_CHG,
-                               .pstate_latency_us = 23.84,
+                               .pstate_latency_us = 11.72,
+                               .sr_exit_time_us = 10.12,
+                               .sr_enter_plus_exit_time_us = 11.48,
                                .valid = true,
                        },
                        {
                                .wm_inst = WM_C,
                                .wm_type = WM_TYPE_PSTATE_CHG,
-                               .pstate_latency_us = 23.84,
+                               .pstate_latency_us = 11.72,
+                               .sr_exit_time_us = 10.12,
+                               .sr_enter_plus_exit_time_us = 11.48,
                                .valid = true,
                        },
                        {
                                .wm_inst = WM_D,
                                .wm_type = WM_TYPE_PSTATE_CHG,
-                               .pstate_latency_us = 23.84,
+                               .pstate_latency_us = 11.72,
+                               .sr_exit_time_us = 10.12,
+                               .sr_enter_plus_exit_time_us = 11.48,
                                .valid = true,
                        },
                },

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index dd3bc37d4eb9c0dd43ad7810c40eb0e4474234e4..818c7a62948471fbfcf064bf13a5f9ac01961931 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -972,6 +972,8 @@ static void calculate_wm_set_for_vlevel(
        pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
 
        dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
+       dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
+       dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
 
        wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
        wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
@@ -987,14 +989,21 @@ static void calculate_wm_set_for_vlevel(
 
 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
 {
+       int i;
+
        kernel_fpu_begin();
        if (dc->bb_overrides.sr_exit_time_ns) {
-               bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
+               for (i = 0; i < WM_SET_COUNT; i++) {
+                         dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
+                                         dc->bb_overrides.sr_exit_time_ns / 1000.0;
+               }
        }
 
        if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
-               bb->sr_enter_plus_exit_time_us =
-                               dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
+               for (i = 0; i < WM_SET_COUNT; i++) {
+                         dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
+                                         dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
+               }
        }
 
        if (dc->bb_overrides.urgent_latency_ns) {

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index f55203e427de4766c41b680ed523cad315cf7159..4aa09fe954c56e8e9ba9c3864026f98f6ddeb71c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -66,6 +66,8 @@ struct wm_range_table_entry {
        unsigned int wm_inst;
        unsigned int wm_type;
        double pstate_latency_us;
+       double sr_exit_time_us;
+       double sr_enter_plus_exit_time_us;
        bool valid;
 };