drm/i915: Index the ring frequency table by HW frequency range

When reporting the frequency table stored in the punit, report the full
range and not just the user restricted frequency range. In the process
keep the code to set the frequency table and read it the same.

v3: As we haven't separated the sb_lock from the pcu_lock yet, there's a
cycle between the pcu_lock and intel_runtime_pm_get.

References: f936ec34dea8 ("drm/i915/skl: Updated the i915_ring_freq_table debugfs function")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> #v1
Link: https://patchwork.freedesktop.org/patch/msgid/20180308142648.4016-2-chris@chris-wilson.co.uk

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 89f7ff2c652ee8b0694f0da2a33dc54d0e3b8402..d8bc1bb30cb4afd7c0617d138984aef5cbadd7ea 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1796,9 +1796,9 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
 {
        struct drm_i915_private *dev_priv = node_to_i915(m->private);
        struct intel_rps *rps = &dev_priv->gt_pm.rps;
-       int ret = 0;
-       int gpu_freq, ia_freq;
        unsigned int max_gpu_freq, min_gpu_freq;
+       int gpu_freq, ia_freq;
+       int ret;
 
        if (!HAS_LLC(dev_priv))
                return -ENODEV;
@@ -1809,13 +1809,12 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
        if (ret)
                goto out;
 
+       min_gpu_freq = rps->min_freq;
+       max_gpu_freq = rps->max_freq;
        if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
                /* Convert GT frequency to 50 HZ units */
-               min_gpu_freq = rps->min_freq_softlimit / GEN9_FREQ_SCALER;
-               max_gpu_freq = rps->max_freq_softlimit / GEN9_FREQ_SCALER;
-       } else {
-               min_gpu_freq = rps->min_freq_softlimit;
-               max_gpu_freq = rps->max_freq_softlimit;
+               min_gpu_freq /= GEN9_FREQ_SCALER;
+               max_gpu_freq /= GEN9_FREQ_SCALER;
        }
 
        seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b8da4dcdd584dec02eb3f0316f3ab366f35c8722..dd5ddb77b3062fc85cfc64f7a2a26ee82ad3bd50 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6918,13 +6918,12 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
        /* convert DDR frequency from units of 266.6MHz to bandwidth */
        min_ring_freq = mult_frac(min_ring_freq, 8, 3);
 
+       min_gpu_freq = rps->min_freq;
+       max_gpu_freq = rps->max_freq;
        if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
                /* Convert GT frequency to 50 HZ units */
-               min_gpu_freq = rps->min_freq / GEN9_FREQ_SCALER;
-               max_gpu_freq = rps->max_freq / GEN9_FREQ_SCALER;
-       } else {
-               min_gpu_freq = rps->min_freq;
-               max_gpu_freq = rps->max_freq;
+               min_gpu_freq /= GEN9_FREQ_SCALER;
+               max_gpu_freq /= GEN9_FREQ_SCALER;
        }
 
        /*