]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
drm/amdgpu: update VCN1(dual instances) fw types ID and VCN ip block type
authorJane Jian <Jane.Jian@amd.com>
Mon, 16 Dec 2019 06:56:35 +0000 (14:56 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 18 Dec 2019 21:33:26 +0000 (16:33 -0500)
Previously there is no VCN1 type ID in psp gfx interface. Also add VCN ip
block type unless the reinit after FLR for sriov would fail.

Signed-off-by: Jane Jian <Jane.Jian@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h

index 2f93adc8f384b141317b39feeb5c0e87b9879542..9d69f2dbcfd933aab5898a138b271a92ec4f46e6 100644 (file)
@@ -2441,7 +2441,8 @@ static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
                AMD_IP_BLOCK_TYPE_GFX,
                AMD_IP_BLOCK_TYPE_SDMA,
                AMD_IP_BLOCK_TYPE_UVD,
-               AMD_IP_BLOCK_TYPE_VCE
+               AMD_IP_BLOCK_TYPE_VCE,
+               AMD_IP_BLOCK_TYPE_VCN
        };
 
        for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
index c14f2ccd0677768fadb69dec721058d83dd789bc..3e293a3c2fbf05c1040e198e17e22f3714afabad 100644 (file)
@@ -1310,6 +1310,9 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
        case AMDGPU_UCODE_ID_VCN:
                *type = GFX_FW_TYPE_VCN;
                break;
+       case AMDGPU_UCODE_ID_VCN1:
+               *type = GFX_FW_TYPE_VCN1;
+               break;
        case AMDGPU_UCODE_ID_DMCU_ERAM:
                *type = GFX_FW_TYPE_DMCU_ERAM;
                break;
index 74a9fe8e0cfb92e2cae2ed3e71bfc358b861079a..36b65797434e506d335b3af071df0ade99fdbd9d 100644 (file)
@@ -242,6 +242,7 @@ enum psp_gfx_fw_type {
        GFX_FW_TYPE_SDMA5                           = 55,   /* SDMA5                    MI      */
        GFX_FW_TYPE_SDMA6                           = 56,   /* SDMA6                    MI      */
        GFX_FW_TYPE_SDMA7                           = 57,   /* SDMA7                    MI      */
+       GFX_FW_TYPE_VCN1                            = 58,   /* VCN1                     MI      */
        GFX_FW_TYPE_MAX
 };