]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
arm64: allwinner: a64: Add devicetree binding for DMA controller
authorStefan Brüns <stefan.bruens@rwth-aachen.de>
Thu, 28 Sep 2017 01:49:23 +0000 (03:49 +0200)
committerVinod Koul <vinod.koul@intel.com>
Mon, 16 Oct 2017 07:01:24 +0000 (12:31 +0530)
The A64 is register compatible with the H3, but has a different number
of dma channels and request ports.

Attach additional properties to the node to allow future reuse of the
compatible for controllers with different number of channels/requests.

If dma-requests is not specified, the register layout defined maximum
of 32 is used.

Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Documentation/devicetree/bindings/dma/sun6i-dma.txt

index 98fbe1a5c6dd3d0cc366227eb2def392b797b4da..9700b1d00fed02ca77abc5c104cab767d7e00641 100644 (file)
@@ -27,6 +27,32 @@ Example:
                #dma-cells = <1>;
        };
 
+------------------------------------------------------------------------------
+For A64 DMA controller:
+
+Required properties:
+- compatible:  "allwinner,sun50i-a64-dma"
+- dma-channels: Number of DMA channels supported by the controller.
+               Refer to Documentation/devicetree/bindings/dma/dma.txt
+- all properties above, i.e. reg, interrupts, clocks, resets and #dma-cells
+
+Optional properties:
+- dma-requests: Number of DMA request signals supported by the controller.
+               Refer to Documentation/devicetree/bindings/dma/dma.txt
+
+Example:
+       dma: dma-controller@1c02000 {
+               compatible = "allwinner,sun50i-a64-dma";
+               reg = <0x01c02000 0x1000>;
+               interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&ccu CLK_BUS_DMA>;
+               dma-channels = <8>;
+               dma-requests = <27>;
+               resets = <&ccu RST_BUS_DMA>;
+               #dma-cells = <1>;
+       };
+------------------------------------------------------------------------------
+
 Clients:
 
 DMA clients connected to the A31 DMA controller must use the format