Merge branches 'clk-gpio-flags', 'clk-tegra', 'clk-rockchip', 'clk-sprd' and 'clk...

 - Make gpio gate clks propagate rate setting up to parent

* clk-gpio-flags:
  clk: clk-gpio: propagate rate change to parent

* clk-tegra: (23 commits)
  clk: tegra: Use match_string() helper to simplify the code
  clk: tegra: Fix build error without CONFIG_PM_SLEEP
  clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP
  clk: tegra: Optimize PLLX restore on Tegra20/30
  clk: tegra: Add suspend and resume support on Tegra210
  clk: tegra: Share clk and rst register defines with Tegra clock driver
  clk: tegra: Use fence_udelay() during PLLU init
  clk: tegra: clk-dfll: Add suspend and resume support
  clk: tegra: clk-super: Add restore-context support
  clk: tegra: clk-super: Fix to enable PLLP branches to CPU
  clk: tegra: periph: Add restore_context support
  clk: tegra: Support for OSC context save and restore
  clk: tegra: pll: Save and restore pll context
  clk: tegra: pllout: Save and restore pllout context
  clk: tegra: divider: Save and restore divider rate
  clk: tegra: Reimplement SOR clocks on Tegra210
  clk: tegra: Reimplement SOR clock on Tegra124
  clk: tegra: Rename sor0_lvds to sor0_out
  clk: tegra: Move SOR0 implementation to Tegra124
  clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRC
  ...

* clk-rockchip:
  clk: rockchip: protect the pclk_usb_grf as critical on px30
  clk: rockchip: add video-related niu clocks as critical on px30
  clk: rockchip: move px30 critical clocks to correct clock controller
  clk: rockchip: Add div50 clocks for px30 sdmmc, emmc, sdio and nandc
  clk: rockchip: Add div50 clock-ids for sdmmc on px30 and nandc
  clk: rockchip: make clk_half_divider_ops static

* clk-sprd:
  clk: sprd: Use IS_ERR() to validate the return value of syscon_regmap_lookup_by_phandle()

* clk-pxa:
  clk: pxa: fix one of the pxa RTC clocks

diff --combined drivers/clk/sprd/common.c
index 37186963d61832d6672cfdc1ae2fe64145ce08db,9d56eac43832acc1f00b85d72a9946f6b3f67fd7,9d56eac43832acc1f00b85d72a9946f6b3f67fd7,9d56eac43832acc1f00b85d72a9946f6b3f67fd7,7ad5ba26dfbaf7d4cae16ac123f6c2c683f96589,9d56eac43832acc1f00b85d72a9946f6b3f67fd7..c0af4779892b77958c1fa99a5ca94c11ee4afa11
--- 1/drivers/clk/sprd/common.c
--- 2/drivers/clk/sprd/common.c
--- 3/drivers/clk/sprd/common.c
--- 4/drivers/clk/sprd/common.c
--- 5/drivers/clk/sprd/common.c
--- 6/drivers/clk/sprd/common.c
+++ b/drivers/clk/sprd/common.c
@@@@@@@ -42,15 -42,17 -42,17 -42,17 -42,17 -42,17 +42,15 @@@@@@@ int sprd_clk_regmap_init(struct platfor
        void __iomem *base;
        struct device_node *node = pdev->dev.of_node;
        struct regmap *regmap;
 -----  struct resource *res;
      
        if (of_find_property(node, "sprd,syscon", NULL)) {
                regmap = syscon_regmap_lookup_by_phandle(node, "sprd,syscon");
---- -          if (IS_ERR_OR_NULL(regmap)) {
++++ +          if (IS_ERR(regmap)) {
                        pr_err("%s: failed to get syscon regmap\n", __func__);
                        return PTR_ERR(regmap);
                }
        } else {
 -----          res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 -----          base = devm_ioremap_resource(&pdev->dev, res);
 +++++          base = devm_platform_ioremap_resource(pdev, 0);
                if (IS_ERR(base))
                        return PTR_ERR(base);