arm64: allwinner: a64: add EHCI0/OHCI0 nodes to A64 DTSI

Allwinner A64 SoC features a pair of EHCI/OHCI controllers that can be
set to wire to USB0 port (the OTG-capable one), which can be used to
provide a better performance in host mode.

Add their device tree nodes.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index c7f669f5884f910c6e4be44ac1dd09a216cb97f0..65a344d9cea4519b94ef5bac6a2fa9b39e2dca89 100644 (file)
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -204,6 +204,28 @@ usbphy: phy@01c19400 {
                        #phy-cells = <1>;
                };
 
+               ehci0: usb@01c1a000 {
+                       compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
+                       reg = <0x01c1a000 0x100>;
+                       interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_BUS_OHCI0>,
+                                <&ccu CLK_BUS_EHCI0>,
+                                <&ccu CLK_USB_OHCI0>;
+                       resets = <&ccu RST_BUS_OHCI0>,
+                                <&ccu RST_BUS_EHCI0>;
+                       status = "disabled";
+               };
+
+               ohci0: usb@01c1a400 {
+                       compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
+                       reg = <0x01c1a400 0x100>;
+                       interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_BUS_OHCI0>,
+                                <&ccu CLK_USB_OHCI0>;
+                       resets = <&ccu RST_BUS_OHCI0>;
+                       status = "disabled";
+               };
+
                ehci1: usb@01c1b000 {
                        compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
                        reg = <0x01c1b000 0x100>;