]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
drm/bridge: Prepare Analogix anx6345 support
authorTorsten Duwe <duwe@lst.de>
Tue, 29 Oct 2019 12:16:57 +0000 (13:16 +0100)
committerMaxime Ripard <maxime@cerno.tech>
Fri, 8 Nov 2019 09:27:53 +0000 (10:27 +0100)
Add bit definitions required for the anx6345 and add a
sanity check in anx_dp_aux_transfer.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20191107135218.01C2168C4E@verein.lst.de
drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.c
drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.h
drivers/gpu/drm/bridge/analogix/analogix-i2c-txcommon.h

index 60707bb5afe78cb86d06da0fa2bcc69ac2e84638..fe40bab215306f8101209f90feeb49308be416a2 100644 (file)
@@ -116,7 +116,7 @@ ssize_t anx_dp_aux_transfer(struct regmap *map_dptx,
        else    /* For non-zero-sized set the length field. */
                ctrl1 |= (msg->size - 1) << SP_AUX_LENGTH_SHIFT;
 
-       if ((msg->request & DP_AUX_I2C_READ) == 0) {
+       if ((msg->size > 0) && ((msg->request & DP_AUX_I2C_READ) == 0)) {
                /* When WRITE | MOT write values to data buffer */
                err = regmap_bulk_write(map_dptx,
                                        SP_DP_BUF_DATA0_REG, buffer,
index db24f72904612256bb9bd01c406d94b8b6991182..663c4bea6e70f0a0ddfb32ccdeacee7f2b46ea77 100644 (file)
 #define SP_CHA_STA                     BIT(2)
 /* Bits for DP System Control Register 3 */
 #define SP_HPD_STATUS                  BIT(6)
+#define SP_HPD_FORCE                   BIT(5)
+#define SP_HPD_CTRL                    BIT(4)
 #define SP_STRM_VALID                  BIT(2)
+#define SP_STRM_FORCE                  BIT(1)
+#define SP_STRM_CTRL                   BIT(0)
 /* Bits for DP System Control Register 4 */
 #define SP_ENHANCED_MODE               BIT(3)
 
 #define SP_LINK_BW_SET_MASK            0x1f
 #define SP_INITIAL_SLIM_M_AUD_SEL      BIT(5)
 
+/* DP Lane Count Setting Register */
+#define SP_DP_LANE_COUNT_SET_REG       0xa1
+
 /* DP Training Pattern Set Register */
 #define SP_DP_TRAINING_PATTERN_SET_REG 0xa2
 
 
 /* DP Link Training Control Register */
 #define SP_DP_LT_CTRL_REG              0xa8
+#define SP_DP_LT_INPROGRESS            0x80
 #define SP_LT_ERROR_TYPE_MASK          0x70
 #  define SP_LT_NO_ERROR               0x00
 #  define SP_LT_AUX_WRITE_ERROR                0x01
index 677e78fb862f96502d572a29f72a19b92d368ef2..3c843497d83595fe5a0e84130a7a0aa183384d38 100644 (file)
 #define SP_VBIT                                BIT(1)
 #define SP_AUDIO_LAYOUT                        BIT(0)
 
+/* Analog Debug Register 1 */
+#define SP_ANALOG_DEBUG1_REG           0xdc
+
 /* Analog Debug Register 2 */
 #define SP_ANALOG_DEBUG2_REG           0xdd
 #define SP_FORCE_SW_OFF_BYPASS         0x20