dt-bindings: phy: Move the Cadence D-PHY bindings

The Cadence D-PHY bindings was defined as part of the DSI block so far.
However, since it's now going to be a separate driver, we need to move the
binding to a file of its own.

Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
index f5725bb6c61ca9bd6aa5cb645c4aa006e468a5e7..525a4bfd86340715d084f3a6c2f363f32797c9cc 100644 (file)
--- a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
+++ b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
@@ -31,28 +31,7 @@ Required subnodes:
 - one subnode per DSI device connected on the DSI bus. Each DSI device should
   contain a reg property encoding its virtual channel.
 
-Cadence DPHY
-============
-
-Cadence DPHY block.
-
-Required properties:
-- compatible: should be set to "cdns,dphy".
-- reg: physical base address and length of the DPHY registers.
-- clocks: DPHY reference clocks.
-- clock-names: must contain "psm" and "pll_ref".
-- #phy-cells: must be set to 0.
-
-
 Example:
-       dphy0: dphy@fd0e0000{
-               compatible = "cdns,dphy";
-               reg = <0x0 0xfd0e0000 0x0 0x1000>;
-               clocks = <&psm_clk>, <&pll_ref_clk>;
-               clock-names = "psm", "pll_ref";
-               #phy-cells = <0>;
-       };
-
        dsi0: dsi@fd0c0000 {
                compatible = "cdns,dsi";
                reg = <0x0 0xfd0c0000 0x0 0x1000>;

diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.txt b/Documentation/devicetree/bindings/phy/cdns,dphy.txt
new file mode 100644 (file)
index 0000000..1095bc4
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/cdns,dphy.txt
@@ -0,0 +1,20 @@
+Cadence DPHY
+============
+
+Cadence DPHY block.
+
+Required properties:
+- compatible: should be set to "cdns,dphy".
+- reg: physical base address and length of the DPHY registers.
+- clocks: DPHY reference clocks.
+- clock-names: must contain "psm" and "pll_ref".
+- #phy-cells: must be set to 0.
+
+Example:
+       dphy0: dphy@fd0e0000{
+               compatible = "cdns,dphy";
+               reg = <0x0 0xfd0e0000 0x0 0x1000>;
+               clocks = <&psm_clk>, <&pll_ref_clk>;
+               clock-names = "psm", "pll_ref";
+               #phy-cells = <0>;
+       };