spi: zynq-qspi: Clarify the select chip function

The code used to assert and de-assert a chip select line is very
complicated for no reason. Simplify the logic by either setting or
resetting the concerned bit, which actually only changes an electrical
state.

Update the comment to reflect that there is no possibility to actually
choose a CS as the default (CS0) will be driven in any case.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/r/20191108140744.1734-6-miquel.raynal@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-zynq-qspi.c b/drivers/spi/spi-zynq-qspi.c
index 70ecefd817f7fdeaf8a164f31b0bc6b4f4b034de..80e51c894eaa8404098164b9356448b469ec1fcf 100644 (file)
--- a/drivers/spi/spi-zynq-qspi.c
+++ b/drivers/spi/spi-zynq-qspi.c
@@ -50,7 +50,6 @@
 #define ZYNQ_QSPI_CONFIG_BDRATE_MASK   GENMASK(5, 3) /* Baud Rate Mask */
 #define ZYNQ_QSPI_CONFIG_CPHA_MASK     BIT(2) /* Clock Phase Control */
 #define ZYNQ_QSPI_CONFIG_CPOL_MASK     BIT(1) /* Clock Polarity Control */
-#define ZYNQ_QSPI_CONFIG_SSCTRL_MASK   BIT(10) /* Slave Select Mask */
 #define ZYNQ_QSPI_CONFIG_FWIDTH_MASK   GENMASK(7, 6) /* FIFO width */
 #define ZYNQ_QSPI_CONFIG_MSTREN_MASK   BIT(0) /* Master Mode */
 
@@ -62,7 +61,7 @@
  */
 #define ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX  GENMASK(2, 0) /* Baud rate maximum */
 #define ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT        3 /* Baud rate divisor shift */
-#define ZYNQ_QSPI_CONFIG_PCS           10 /* Peripheral Chip Select */
+#define ZYNQ_QSPI_CONFIG_PCS           BIT(10) /* Peripheral Chip Select */
 
 /*
  * QSPI Interrupt Registers bit Masks
@@ -287,16 +286,12 @@ static void zynq_qspi_chipselect(struct spi_device *spi, bool assert)
        struct zynq_qspi *xqspi = spi_controller_get_devdata(ctlr);
        u32 config_reg;
 
+       /* Ground the line to assert the CS */
        config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);
-       if (assert) {
-               /* Select the slave */
-               config_reg &= ~ZYNQ_QSPI_CONFIG_SSCTRL_MASK;
-               config_reg |= (((~(BIT(spi->chip_select))) <<
-                               ZYNQ_QSPI_CONFIG_PCS) &
-                               ZYNQ_QSPI_CONFIG_SSCTRL_MASK);
-       } else {
-               config_reg |= ZYNQ_QSPI_CONFIG_SSCTRL_MASK;
-       }
+       if (assert)
+               config_reg &= ~ZYNQ_QSPI_CONFIG_PCS;
+       else
+               config_reg |= ZYNQ_QSPI_CONFIG_PCS;
 
        zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);
 }