drm/amd/powerplay: issue proper hdp flush for table transferring

Guard the content consistence between the view of GPU and CPU
during the table transferring.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 9320cf3ef036997a463e3f045dbb164653e0f74e..b4cc0dc001896635c0981fa34fb7a33205cb5566 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -529,8 +529,14 @@ int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int
 
        table_size = smu_table->tables[table_index].size;
 
-       if (drv2smu)
+       if (drv2smu) {
                memcpy(table->cpu_addr, table_data, table_size);
+               /*
+                * Flush hdp cache: to guard the content seen by
+                * GPU is consitent with CPU.
+                */
+               amdgpu_asic_flush_hdp(adev, NULL);
+       }
 
        ret = smu_send_smc_msg_with_param(smu, drv2smu ?
                                          SMU_MSG_TransferTableDram2Smu :
@@ -539,11 +545,10 @@ int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int
        if (ret)
                return ret;
 
-       /* flush hdp cache */
-       adev->nbio.funcs->hdp_flush(adev, NULL);
-
-       if (!drv2smu)
+       if (!drv2smu) {
+               amdgpu_asic_flush_hdp(adev, NULL);
                memcpy(table_data, table->cpu_addr, table_size);
+       }
 
        return ret;
 }

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
index aa0ee2b46135421477deb36d6f65a810b33ebc37..2319400a3fcb60d046323d422e7c9484ccfeaa32 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
@@ -137,7 +137,7 @@ static int smu10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
                        priv->smu_tables.entry[table_id].table_id);
 
        /* flush hdp cache */
-       adev->nbio.funcs->hdp_flush(adev, NULL);
+       amdgpu_asic_flush_hdp(adev, NULL);
 
        memcpy(table, (uint8_t *)priv->smu_tables.entry[table_id].table,
                        priv->smu_tables.entry[table_id].size);
@@ -150,6 +150,7 @@ static int smu10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
 {
        struct smu10_smumgr *priv =
                        (struct smu10_smumgr *)(hwmgr->smu_backend);
+       struct amdgpu_device *adev = hwmgr->adev;
 
        PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
                        "Invalid SMU Table ID!", return -EINVAL;);
@@ -161,6 +162,8 @@ static int smu10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
        memcpy(priv->smu_tables.entry[table_id].table, table,
                        priv->smu_tables.entry[table_id].size);
 
+       amdgpu_asic_flush_hdp(adev, NULL);
+
        smu10_send_msg_to_smc_with_parameter(hwmgr,
                        PPSMC_MSG_SetDriverDramAddrHigh,
                        upper_32_bits(priv->smu_tables.entry[table_id].mc_addr));

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
index 39427ca32a150dc5f9edf17e84177198967bf757..715564009089615e6ce9b0dbc86ec2fe78307a9f 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
@@ -58,7 +58,7 @@ static int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
                        priv->smu_tables.entry[table_id].table_id);
 
        /* flush hdp cache */
-       adev->nbio.funcs->hdp_flush(adev, NULL);
+       amdgpu_asic_flush_hdp(adev, NULL);
 
        memcpy(table, priv->smu_tables.entry[table_id].table,
                        priv->smu_tables.entry[table_id].size);
@@ -70,6 +70,7 @@ static int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
                uint8_t *table, int16_t table_id)
 {
        struct vega10_smumgr *priv = hwmgr->smu_backend;
+       struct amdgpu_device *adev = hwmgr->adev;
 
        /* under sriov, vbios or hypervisor driver
         * has already copy table to smc so here only skip it
@@ -87,6 +88,8 @@ static int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
        memcpy(priv->smu_tables.entry[table_id].table, table,
                        priv->smu_tables.entry[table_id].size);
 
+       amdgpu_asic_flush_hdp(adev, NULL);
+
        smu9_send_msg_to_smc_with_parameter(hwmgr,
                        PPSMC_MSG_SetDriverDramAddrHigh,
                        upper_32_bits(priv->smu_tables.entry[table_id].mc_addr));

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
index 90c782c132d255a96426cf303f8eb4c09eef3f0b..a3915bfcce8103c05b9fb50ae2c5a9dca30bc832 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
@@ -66,7 +66,7 @@ static int vega12_copy_table_from_smc(struct pp_hwmgr *hwmgr,
                        return -EINVAL);
 
        /* flush hdp cache */
-       adev->nbio.funcs->hdp_flush(adev, NULL);
+       amdgpu_asic_flush_hdp(adev, NULL);
 
        memcpy(table, priv->smu_tables.entry[table_id].table,
                        priv->smu_tables.entry[table_id].size);
@@ -84,6 +84,7 @@ static int vega12_copy_table_to_smc(struct pp_hwmgr *hwmgr,
 {
        struct vega12_smumgr *priv =
                        (struct vega12_smumgr *)(hwmgr->smu_backend);
+       struct amdgpu_device *adev = hwmgr->adev;
 
        PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,
                        "Invalid SMU Table ID!", return -EINVAL);
@@ -95,6 +96,8 @@ static int vega12_copy_table_to_smc(struct pp_hwmgr *hwmgr,
        memcpy(priv->smu_tables.entry[table_id].table, table,
                        priv->smu_tables.entry[table_id].size);
 
+       amdgpu_asic_flush_hdp(adev, NULL);
+
        PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr,
                        PPSMC_MSG_SetDriverDramAddrHigh,
                        upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0,

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
index f604612f411f3a1f2c2e52eebc4ef3698a0a55f7..0db57fb83d307fdff95425c9d48d42f68eea7172 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
@@ -189,7 +189,7 @@ static int vega20_copy_table_from_smc(struct pp_hwmgr *hwmgr,
                        return ret);
 
        /* flush hdp cache */
-       adev->nbio.funcs->hdp_flush(adev, NULL);
+       amdgpu_asic_flush_hdp(adev, NULL);
 
        memcpy(table, priv->smu_tables.entry[table_id].table,
                        priv->smu_tables.entry[table_id].size);
@@ -207,6 +207,7 @@ static int vega20_copy_table_to_smc(struct pp_hwmgr *hwmgr,
 {
        struct vega20_smumgr *priv =
                        (struct vega20_smumgr *)(hwmgr->smu_backend);
+       struct amdgpu_device *adev = hwmgr->adev;
        int ret = 0;
 
        PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,
@@ -219,6 +220,8 @@ static int vega20_copy_table_to_smc(struct pp_hwmgr *hwmgr,
        memcpy(priv->smu_tables.entry[table_id].table, table,
                        priv->smu_tables.entry[table_id].size);
 
+       amdgpu_asic_flush_hdp(adev, NULL);
+
        PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
                        PPSMC_MSG_SetDriverDramAddrHigh,
                        upper_32_bits(priv->smu_tables.entry[table_id].mc_addr))) == 0,
@@ -242,11 +245,14 @@ int vega20_set_activity_monitor_coeff(struct pp_hwmgr *hwmgr,
 {
        struct vega20_smumgr *priv =
                        (struct vega20_smumgr *)(hwmgr->smu_backend);
+       struct amdgpu_device *adev = hwmgr->adev;
        int ret = 0;
 
        memcpy(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].table, table,
                        priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].size);
 
+       amdgpu_asic_flush_hdp(adev, NULL);
+
        PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
                        PPSMC_MSG_SetDriverDramAddrHigh,
                        upper_32_bits(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr))) == 0,
@@ -290,7 +296,7 @@ int vega20_get_activity_monitor_coeff(struct pp_hwmgr *hwmgr,
                        return ret);
 
        /* flush hdp cache */
-       adev->nbio.funcs->hdp_flush(adev, NULL);
+       amdgpu_asic_flush_hdp(adev, NULL);
 
        memcpy(table, priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].table,
                        priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].size);