net: switch to using PHY_INTERFACE_MODE_10GBASER rather than 10GKR

Switch network drivers, phy drivers, and SFP/phylink over to use the
more correct 10GBASE-R, rather than 10GBASE-KR. 10GBASE-KR is backplane
ethernet, which is 10GBASE-R with autonegotiation on top, which our
current usage on the affected platforms does not have.

The only remaining user of PHY_INTERFACE_MODE_10GKR is the Aquantia
PHY, which has a separate mode for 10GBASE-KR.

For Marvell mvpp2, we detect 10GBASE-KR, and rewrite it to 10GBASE-R
for compatibility with existing DT - this is the only network driver
at present that makes use of PHY_INTERFACE_MODE_10GKR.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index cd32c7196a7f97354558bf282e8a536969c31186..72133cbe55d4e8b6b8ecf0238098b4df50b4d018 100644 (file)
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -1114,7 +1114,7 @@ mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
 /* Port configuration routines */
 static bool mvpp2_is_xlg(phy_interface_t interface)
 {
-       return interface == PHY_INTERFACE_MODE_10GKR ||
+       return interface == PHY_INTERFACE_MODE_10GBASER ||
               interface == PHY_INTERFACE_MODE_XAUI;
 }
 
@@ -1200,7 +1200,7 @@ static int mvpp22_gop_init(struct mvpp2_port *port)
        case PHY_INTERFACE_MODE_2500BASEX:
                mvpp22_gop_init_sgmii(port);
                break;
-       case PHY_INTERFACE_MODE_10GKR:
+       case PHY_INTERFACE_MODE_10GBASER:
                if (port->gop_id != 0)
                        goto invalid_conf;
                mvpp22_gop_init_10gkr(port);
@@ -1649,7 +1649,7 @@ static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port)
        xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
 
        switch (port->phy_interface) {
-       case PHY_INTERFACE_MODE_10GKR:
+       case PHY_INTERFACE_MODE_10GBASER:
                val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
                val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX |
                       MAC_CLK_RESET_SD_TX;
@@ -4758,7 +4758,7 @@ static void mvpp2_phylink_validate(struct phylink_config *config,
 
        /* Invalid combinations */
        switch (state->interface) {
-       case PHY_INTERFACE_MODE_10GKR:
+       case PHY_INTERFACE_MODE_10GBASER:
        case PHY_INTERFACE_MODE_XAUI:
                if (port->gop_id != 0)
                        goto empty_set;
@@ -4780,7 +4780,7 @@ static void mvpp2_phylink_validate(struct phylink_config *config,
        phylink_set(mask, Asym_Pause);
 
        switch (state->interface) {
-       case PHY_INTERFACE_MODE_10GKR:
+       case PHY_INTERFACE_MODE_10GBASER:
        case PHY_INTERFACE_MODE_XAUI:
        case PHY_INTERFACE_MODE_NA:
                if (port->gop_id == 0) {
@@ -5247,6 +5247,15 @@ static int mvpp2_port_probe(struct platform_device *pdev,
                goto err_free_netdev;
        }
 
+       /*
+        * Rewrite 10GBASE-KR to 10GBASE-R for compatibility with existing DT.
+        * Existing usage of 10GBASE-KR is not correct; no backplane
+        * negotiation is done, and this driver does not actually support
+        * 10GBASE-KR.
+        */
+       if (phy_mode == PHY_INTERFACE_MODE_10GKR)
+               phy_mode = PHY_INTERFACE_MODE_10GBASER;
+
        if (port_node) {
                comphy = devm_of_phy_get(&pdev->dev, port_node, NULL);
                if (IS_ERR(comphy)) {

diff --git a/drivers/net/phy/aquantia_main.c b/drivers/net/phy/aquantia_main.c
index 975789d9349dc5f72184af47e5c132e2a19c265b..31927b2c7d5af6d6c0d270693064a8287dafc7ba 100644 (file)
--- a/drivers/net/phy/aquantia_main.c
+++ b/drivers/net/phy/aquantia_main.c
@@ -358,9 +358,11 @@ static int aqr107_read_status(struct phy_device *phydev)
 
        switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
        case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
-       case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
                phydev->interface = PHY_INTERFACE_MODE_10GKR;
                break;
+       case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
+               phydev->interface = PHY_INTERFACE_MODE_10GBASER;
+               break;
        case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
                phydev->interface = PHY_INTERFACE_MODE_USXGMII;
                break;
@@ -493,7 +495,8 @@ static int aqr107_config_init(struct phy_device *phydev)
            phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
            phydev->interface != PHY_INTERFACE_MODE_XGMII &&
            phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
-           phydev->interface != PHY_INTERFACE_MODE_10GKR)
+           phydev->interface != PHY_INTERFACE_MODE_10GKR &&
+           phydev->interface != PHY_INTERFACE_MODE_10GBASER)
                return -ENODEV;
 
        WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,

diff --git a/drivers/net/phy/bcm84881.c b/drivers/net/phy/bcm84881.c
index db59911b9b3ca2821f7bc4c2ce800b005ea3a210..14d55a77eb28afcf1bc2ee4ef64844d860b016fa 100644 (file)
--- a/drivers/net/phy/bcm84881.c
+++ b/drivers/net/phy/bcm84881.c
@@ -53,7 +53,7 @@ static int bcm84881_config_init(struct phy_device *phydev)
        switch (phydev->interface) {
        case PHY_INTERFACE_MODE_SGMII:
        case PHY_INTERFACE_MODE_2500BASEX:
-       case PHY_INTERFACE_MODE_10GKR:
+       case PHY_INTERFACE_MODE_10GBASER:
                break;
        default:
                return -ENODEV;
@@ -218,7 +218,7 @@ static int bcm84881_read_status(struct phy_device *phydev)
        if (mode == 1 || mode == 2)
                phydev->interface = PHY_INTERFACE_MODE_SGMII;
        else if (mode == 3)
-               phydev->interface = PHY_INTERFACE_MODE_10GKR;
+               phydev->interface = PHY_INTERFACE_MODE_10GBASER;
        else if (mode == 4)
                phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
        switch (mode & 7) {

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 512f27b0b5cd3afed4cbf5984434dadcb43f4888..64c9f3bba2cde3414a2a59b5988833415a53a7de 100644 (file)
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -216,7 +216,7 @@ static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
        sfp_parse_support(phydev->sfp_bus, id, support);
        iface = sfp_select_interface(phydev->sfp_bus, support);
 
-       if (iface != PHY_INTERFACE_MODE_10GKR) {
+       if (iface != PHY_INTERFACE_MODE_10GBASER) {
                dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
                return -EINVAL;
        }
@@ -304,7 +304,7 @@ static int mv3310_config_init(struct phy_device *phydev)
            phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
            phydev->interface != PHY_INTERFACE_MODE_XAUI &&
            phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
-           phydev->interface != PHY_INTERFACE_MODE_10GKR)
+           phydev->interface != PHY_INTERFACE_MODE_10GBASER)
                return -ENODEV;
 
        return 0;
@@ -386,16 +386,17 @@ static void mv3310_update_interface(struct phy_device *phydev)
 {
        if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
             phydev->interface == PHY_INTERFACE_MODE_2500BASEX ||
-            phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) {
+            phydev->interface == PHY_INTERFACE_MODE_10GBASER) &&
+           phydev->link) {
                /* The PHY automatically switches its serdes interface (and
-                * active PHYXS instance) between Cisco SGMII, 10GBase-KR and
+                * active PHYXS instance) between Cisco SGMII, 10GBase-R and
                 * 2500BaseX modes according to the speed.  Florian suggests
                 * setting phydev->interface to communicate this to the MAC.
                 * Only do this if we are already in one of the above modes.
                 */
                switch (phydev->speed) {
                case SPEED_10000:
-                       phydev->interface = PHY_INTERFACE_MODE_10GKR;
+                       phydev->interface = PHY_INTERFACE_MODE_10GBASER;
                        break;
                case SPEED_2500:
                        phydev->interface = PHY_INTERFACE_MODE_2500BASEX;

diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 3f7fa634134a1de4e928be06c75f0ecd13600fd9..1edca9725370be0a2a83ea490083dc6bb93767b8 100644 (file)
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -298,6 +298,7 @@ static int phylink_parse_mode(struct phylink *pl, struct fwnode_handle *fwnode)
                        break;
 
                case PHY_INTERFACE_MODE_10GKR:
+               case PHY_INTERFACE_MODE_10GBASER:
                        phylink_set(pl->supported, 10baseT_Half);
                        phylink_set(pl->supported, 10baseT_Full);
                        phylink_set(pl->supported, 100baseT_Half);

diff --git a/drivers/net/phy/sfp-bus.c b/drivers/net/phy/sfp-bus.c
index 06e6429b8b7164e4e9f336ef2bb84dee69dc0d8c..d949ea7b4f8c29c2c2f64e0b19c32b34fe50ee87 100644 (file)
--- a/drivers/net/phy/sfp-bus.c
+++ b/drivers/net/phy/sfp-bus.c
@@ -373,7 +373,7 @@ phy_interface_t sfp_select_interface(struct sfp_bus *bus,
            phylink_test(link_modes, 10000baseLRM_Full) ||
            phylink_test(link_modes, 10000baseER_Full) ||
            phylink_test(link_modes, 10000baseT_Full))
-               return PHY_INTERFACE_MODE_10GKR;
+               return PHY_INTERFACE_MODE_10GBASER;
 
        if (phylink_test(link_modes, 2500baseX_Full))
                return PHY_INTERFACE_MODE_2500BASEX;

diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index e3b87c94aaf695af303ab8bd87fc34df8adc0ec6..e41367f36ee1c96ecd8059d2d62e330f636a07a4 100644 (file)
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -221,7 +221,7 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
        ETH_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
        ETH_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
        ETH_CONF(2, 0, PHY_INTERFACE_MODE_RXAUI, 0x1, COMPHY_FW_MODE_RXAUI),
-       ETH_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1, COMPHY_FW_MODE_XFI),
+       ETH_CONF(2, 0, PHY_INTERFACE_MODE_10GBASER, 0x1, COMPHY_FW_MODE_XFI),
        GEN_CONF(2, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
        GEN_CONF(2, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
        GEN_CONF(2, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
@@ -235,14 +235,14 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
        /* lane 4 */
        ETH_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
        ETH_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
-       ETH_CONF(4, 0, PHY_INTERFACE_MODE_10GKR, 0x2, COMPHY_FW_MODE_XFI),
+       ETH_CONF(4, 0, PHY_INTERFACE_MODE_10GBASER, 0x2, COMPHY_FW_MODE_XFI),
        ETH_CONF(4, 0, PHY_INTERFACE_MODE_RXAUI, 0x2, COMPHY_FW_MODE_RXAUI),
        GEN_CONF(4, 0, PHY_MODE_USB_DEVICE_SS, COMPHY_FW_MODE_USB3D),
        GEN_CONF(4, 1, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
        GEN_CONF(4, 1, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
        ETH_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
        ETH_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_HS_SGMII),
-       ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GKR, -1, COMPHY_FW_MODE_XFI),
+       ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GBASER, -1, COMPHY_FW_MODE_XFI),
        /* lane 5 */
        ETH_CONF(5, 1, PHY_INTERFACE_MODE_RXAUI, 0x2, COMPHY_FW_MODE_RXAUI),
        GEN_CONF(5, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
@@ -342,7 +342,7 @@ static int mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane)
                 MVEBU_COMPHY_SERDES_CFG0_RXAUI_MODE);
 
        switch (lane->submode) {
-       case PHY_INTERFACE_MODE_10GKR:
+       case PHY_INTERFACE_MODE_10GBASER:
                val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xe) |
                       MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xe);
                break;
@@ -417,7 +417,7 @@ static int mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane)
        /* refclk selection */
        val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));
        val &= ~MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL;
-       if (lane->submode == PHY_INTERFACE_MODE_10GKR)
+       if (lane->submode == PHY_INTERFACE_MODE_10GBASER)
                val |= MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE;
        writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));
 
@@ -564,7 +564,7 @@ static int mvebu_comphy_set_mode_rxaui(struct phy *phy)
        return mvebu_comphy_init_plls(lane);
 }
 
-static int mvebu_comphy_set_mode_10gkr(struct phy *phy)
+static int mvebu_comphy_set_mode_10gbaser(struct phy *phy)
 {
        struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
        struct mvebu_comphy_priv *priv = lane->priv;
@@ -735,8 +735,8 @@ static int mvebu_comphy_power_on_legacy(struct phy *phy)
        case PHY_INTERFACE_MODE_RXAUI:
                ret = mvebu_comphy_set_mode_rxaui(phy);
                break;
-       case PHY_INTERFACE_MODE_10GKR:
-               ret = mvebu_comphy_set_mode_10gkr(phy);
+       case PHY_INTERFACE_MODE_10GBASER:
+               ret = mvebu_comphy_set_mode_10gbaser(phy);
                break;
        default:
                return -ENOTSUPP;
@@ -782,8 +782,8 @@ static int mvebu_comphy_power_on(struct phy *phy)
                                lane->id);
                        fw_speed = COMPHY_FW_SPEED_3125;
                        break;
-               case PHY_INTERFACE_MODE_10GKR:
-                       dev_dbg(priv->dev, "set lane %d to 10G-KR mode\n",
+               case PHY_INTERFACE_MODE_10GBASER:
+                       dev_dbg(priv->dev, "set lane %d to 10GBASE-R mode\n",
                                lane->id);
                        fw_speed = COMPHY_FW_SPEED_103125;
                        break;