drm/i915: Fix pixel clock and crtc clock config mismatch

In case of dual link mode, the mode clock that we get
from the VBT is halved.

v2: Simplify the calculation (Jani).

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1556809862-31203-4-git-send-email-vandita.kulkarni@intel.com

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index e94f951a8626a193325265ff5387993caa3132f4..1e240ad665b57574a0181093019af0a1211e2b17 100644 (file)
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1212,7 +1212,11 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
        /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
        pipe_config->port_clock =
                cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);
+
        pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
+       if (intel_dsi->dual_link)
+               pipe_config->base.adjusted_mode.crtc_clock *= 2;
+
        gen11_dsi_get_timings(encoder, pipe_config);
        pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
        pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);