drm/amd/display: Register VUPDATE_NO_LOCK interrupts for DCN2

[Why]
These are needed to send back DRM vblank events in the case where VRR
is on. Without the interrupt enabled we're deferring the events into the
vblank queue and userspace is left waiting forever to get back the
events they need.

Found using igt@kms_vrr - the test fails immediately due to vblank
timeout.

[How]
Register them the same way we're handling it for DCN1.

This fixes igt@kms_vrr for DCN2.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: David Francis <David.Francis@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
index 3cc0f2a1f77cc69b33188a6299dfceba60804a64..5db29bf582d31b19e2f9fa84604a594ca2bf442e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
@@ -167,6 +167,11 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
        .ack = NULL
 };
 
+static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
+       .set = NULL,
+       .ack = NULL
+};
+
 #undef BASE_INNER
 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 
@@ -221,12 +226,15 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
                .funcs = &pflip_irq_info_funcs\
        }
 
-#define vupdate_int_entry(reg_num)\
+/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
+ * of DCE's DC_IRQ_SOURCE_VUPDATEx.
+ */
+#define vupdate_no_lock_int_entry(reg_num)\
        [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
                IRQ_REG_ENTRY(OTG, reg_num,\
-                       OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\
-                       OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\
-               .funcs = &vblank_irq_info_funcs\
+                       OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
+                       OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
+               .funcs = &vupdate_no_lock_irq_info_funcs\
        }
 
 #define vblank_int_entry(reg_num)\
@@ -333,12 +341,12 @@ irq_source_info_dcn20[DAL_IRQ_SOURCES_NUMBER] = {
        dc_underflow_int_entry(6),
        [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
        [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
-       vupdate_int_entry(0),
-       vupdate_int_entry(1),
-       vupdate_int_entry(2),
-       vupdate_int_entry(3),
-       vupdate_int_entry(4),
-       vupdate_int_entry(5),
+       vupdate_no_lock_int_entry(0),
+       vupdate_no_lock_int_entry(1),
+       vupdate_no_lock_int_entry(2),
+       vupdate_no_lock_int_entry(3),
+       vupdate_no_lock_int_entry(4),
+       vupdate_no_lock_int_entry(5),
        vblank_int_entry(0),
        vblank_int_entry(1),
        vblank_int_entry(2),