]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
arm64: dts: fsl: Remove unused properties from FSL QSPI nodes
authorFrieder Schrempf <frieder.schrempf@kontron.de>
Wed, 20 Mar 2019 14:38:04 +0000 (14:38 +0000)
committerShawn Guo <shawnguo@kernel.org>
Fri, 22 Mar 2019 02:20:38 +0000 (10:20 +0800)
After switching to the new FSL QSPI driver the properties
'fsl,qspi-has-second-chip' and 'big-endian' are not used anymore.

The driver now uses the 'reg' property to determine the bus and
the chipselect. The endianness is selected by the driver depending
on which SoC is used.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi

index 6fd6116509cc79e2c745be27e74a3c7a480f56ad..2fb8138c6bb049c776fe38d75dd51c5176a7c07a 100644 (file)
@@ -296,7 +296,6 @@ qspi: spi@1550000 {
                        interrupts = <0 99 0x4>;
                        clock-names = "qspi_en", "qspi";
                        clocks = <&clockgen 4 0>, <&clockgen 4 0>;
-                       big-endian;
                        status = "disabled";
                };
 
index cb7185014d3a61f4c03ecfbf58ac0fc35474d728..b0ef08b090ddb1161b570701a850132a64ca359f 100644 (file)
@@ -215,8 +215,6 @@ qspi: spi@1550000 {
                        interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
                        clock-names = "qspi_en", "qspi";
                        clocks = <&clockgen 4 1>, <&clockgen 4 1>;
-                       big-endian;
-                       fsl,qspi-has-second-chip;
                        status = "disabled";
                };