]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
ARM: dts: r8a77470: Add SCIF DMA support
authorBiju Das <biju.das@bp.renesas.com>
Tue, 24 Apr 2018 08:56:04 +0000 (09:56 +0100)
committerSimon Horman <horms+renesas@verge.net.au>
Wed, 25 Apr 2018 06:51:21 +0000 (08:51 +0200)
Add SCIF DMA support for R8A77470 SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm/boot/dts/r8a77470.dtsi

index 39549f28be852dc62a76f8b653bfeef8bf5000ac..baec3cae49d5f1e7f2522273d762a25286b0ba2a 100644 (file)
@@ -198,6 +198,9 @@ scif0: serial@e6e60000 {
                        clocks = <&cpg CPG_MOD 721>,
                                 <&cpg CPG_CORE 5>, <&scif_clk>;
                        clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+                              <&dmac1 0x29>, <&dmac1 0x2a>;
+                       dma-names = "tx", "rx", "tx", "rx";
                        power-domains = <&sysc 32>;
                        resets = <&cpg 721>;
                        status = "disabled";
@@ -211,6 +214,9 @@ scif1: serial@e6e68000 {
                        clocks = <&cpg CPG_MOD 720>,
                                 <&cpg CPG_CORE 5>, <&scif_clk>;
                        clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+                              <&dmac1 0x2d>, <&dmac1 0x2e>;
+                       dma-names = "tx", "rx", "tx", "rx";
                        power-domains = <&sysc 32>;
                        resets = <&cpg 720>;
                        status = "disabled";
@@ -224,6 +230,9 @@ scif2: serial@e6e58000 {
                        clocks = <&cpg CPG_MOD 719>,
                                 <&cpg CPG_CORE 5>, <&scif_clk>;
                        clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+                              <&dmac1 0x2b>, <&dmac1 0x2c>;
+                       dma-names = "tx", "rx", "tx", "rx";
                        power-domains = <&sysc 32>;
                        resets = <&cpg 719>;
                        status = "disabled";
@@ -237,6 +246,9 @@ scif3: serial@e6ea8000 {
                        clocks = <&cpg CPG_MOD 718>,
                                 <&cpg CPG_CORE 5>, <&scif_clk>;
                        clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+                              <&dmac1 0x2f>, <&dmac1 0x30>;
+                       dma-names = "tx", "rx", "tx", "rx";
                        power-domains = <&sysc 32>;
                        resets = <&cpg 718>;
                        status = "disabled";
@@ -250,6 +262,9 @@ scif4: serial@e6ee0000 {
                        clocks = <&cpg CPG_MOD 715>,
                                 <&cpg CPG_CORE 5>, <&scif_clk>;
                        clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+                              <&dmac1 0xfb>, <&dmac1 0xfc>;
+                       dma-names = "tx", "rx", "tx", "rx";
                        power-domains = <&sysc 32>;
                        resets = <&cpg 715>;
                        status = "disabled";
@@ -263,6 +278,9 @@ scif5: serial@e6ee8000 {
                        clocks = <&cpg CPG_MOD 714>,
                                 <&cpg CPG_CORE 5>, <&scif_clk>;
                        clock-names = "fck", "brg_int", "scif_clk";
+                       dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+                              <&dmac1 0xfd>, <&dmac1 0xfe>;
+                       dma-names = "tx", "rx", "tx", "rx";
                        power-domains = <&sysc 32>;
                        resets = <&cpg 714>;
                        status = "disabled";