ret = clk_hw_register(NULL, &pll_clk->hw);
if (ret) {
- pr_err("failed to register %s clock\n", node->name);
+ pr_err("failed to register %pOFn clock\n", node);
goto err_unmap_lock;
}
ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clk->hw);
if (ret) {
- pr_err("failed to add hw provider for %s clock\n", node->name);
+ pr_err("failed to add hw provider for %pOFn clock\n", node);
goto err_unregister_clk;
}
ret = of_address_to_resource(node, 0, &res);
if (ret) {
- pr_err("%s: no valid CCU registers found for %s\n", __func__,
- node->name);
+ pr_err("%s: no valid CCU registers found for %pOFn\n", __func__,
+ node);
goto out_err;
}
range = resource_size(&res);
if (range > (resource_size_t)U32_MAX) {
- pr_err("%s: address range too large for %s\n", __func__,
- node->name);
+ pr_err("%s: address range too large for %pOFn\n", __func__,
+ node);
goto out_err;
}
ccu->range = (u32)range;
if (!ccu_data_valid(ccu)) {
- pr_err("%s: ccu data not valid for %s\n", __func__, node->name);
+ pr_err("%s: ccu data not valid for %pOFn\n", __func__, node);
goto out_err;
}
ccu->base = ioremap(res.start, ccu->range);
if (!ccu->base) {
- pr_err("%s: unable to map CCU registers for %s\n", __func__,
- node->name);
+ pr_err("%s: unable to map CCU registers for %pOFn\n", __func__,
+ node);
goto out_err;
}
ccu->node = of_node_get(node);
ret = of_clk_add_hw_provider(node, of_clk_kona_onecell_get, ccu);
if (ret) {
- pr_err("%s: error adding ccu %s as provider (%d)\n", __func__,
- node->name, ret);
+ pr_err("%s: error adding ccu %pOFn as provider (%d)\n", __func__,
+ node, ret);
goto out_err;
}
if (!kona_ccu_init(ccu))
- pr_err("Broadcom %s initialization had errors\n", node->name);
+ pr_err("Broadcom %pOFn initialization had errors\n", node);
return;
out_err:
kona_ccu_teardown(ccu);
- pr_err("Broadcom %s setup aborted\n", node->name);
+ pr_err("Broadcom %pOFn setup aborted\n", node);
}
base = of_io_request_and_map(np, 0, np->name);
if (IS_ERR(base))
- panic("%s: unable to map resource", np->name);
+ panic("%pOFn: unable to map resource", np);
/* register pll */
rate = (ioread32(base + HW_SYSPLLCTRL) & 0xffff) * 1000000;
ref_clk, 0, rate, accuracy);
if (IS_ERR(hw))
- panic("%s: can't register REFCLK. Check DT!", np->name);
+ panic("%pOFn: can't register REFCLK. Check DT!", np);
for (n = 0; n < ARRAY_SIZE(asm9260_mux_clks); n++) {
const struct asm9260_mux_clock *mc = &asm9260_mux_clks[n];
/* Register PLL clocks */
for (i = 0; i < data->chip_info->num_plls; ++i) {
- pll_clk_name[i] = kasprintf(GFP_KERNEL, "%s.pll%d",
- client->dev.of_node->name, i);
+ pll_clk_name[i] = kasprintf(GFP_KERNEL, "%pOFn.pll%d",
+ client->dev.of_node, i);
init.name = pll_clk_name[i];
data->pll[i].chip = data;
data->pll[i].hw.init = &init;
init.flags = 0;
init.num_parents = 1;
init.parent_names = &parent_name; /* Mux Y1 to input */
- init.name = kasprintf(GFP_KERNEL, "%s.Y1", client->dev.of_node->name);
+ init.name = kasprintf(GFP_KERNEL, "%pOFn.Y1", client->dev.of_node);
data->clk[0].chip = data;
data->clk[0].hw.init = &init;
data->clk[0].index = 0;
init.flags = CLK_SET_RATE_PARENT;
init.num_parents = 1;
for (i = 1; i < data->chip_info->num_outputs; ++i) {
- init.name = kasprintf(GFP_KERNEL, "%s.Y%d",
- client->dev.of_node->name, i+1);
+ init.name = kasprintf(GFP_KERNEL, "%pOFn.Y%d",
+ client->dev.of_node, i+1);
data->clk[i].chip = data;
data->clk[i].hw.init = &init;
data->clk[i].index = i;
int ret;
if (of_property_read_u32(node, "clock-div", &div)) {
- pr_err("%s Fixed factor clock <%s> must have a clock-div property\n",
- __func__, node->name);
+ pr_err("%s Fixed factor clock <%pOFn> must have a clock-div property\n",
+ __func__, node);
return ERR_PTR(-EIO);
}
if (of_property_read_u32(node, "clock-mult", &mult)) {
- pr_err("%s Fixed factor clock <%s> must have a clock-mult property\n",
- __func__, node->name);
+ pr_err("%s Fixed factor clock <%pOFn> must have a clock-mult property\n",
+ __func__, node);
return ERR_PTR(-EIO);
}
if (IS_ERR(gpiod)) {
ret = PTR_ERR(gpiod);
if (ret == -EPROBE_DEFER)
- pr_debug("%s: %s: GPIOs not yet available, retry later\n",
- node->name, __func__);
+ pr_debug("%pOFn: %s: GPIOs not yet available, retry later\n",
+ node, __func__);
else
- pr_err("%s: %s: Can't get '%s' named GPIO property\n",
- node->name, __func__,
+ pr_err("%pOFn: %s: Can't get '%s' named GPIO property\n",
+ node, __func__,
gpio_name);
return ret;
}
ret = clk_hw_register(NULL, &pll_clk->hw);
if (ret) {
- pr_err("failed to register %s clock\n", node->name);
+ pr_err("failed to register %pOFn clock\n", node);
goto err_unmap_spec_regs;
}
ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clk->hw);
if (ret) {
- pr_err("failed to add hw provider for %s clock\n", node->name);
+ pr_err("failed to add hw provider for %pOFn clock\n", node);
goto err_unmap_spec_regs;
}
}
src_base = of_iomap(np, 0);
if (!src_base) {
- pr_err("%s: must have src parent node with REGS (%s)\n",
- __func__, np->name);
+ pr_err("%s: must have src parent node with REGS (%pOFn)\n",
+ __func__, np);
return;
}
ret = of_address_to_resource(clk_np, 0, &res);
if (ret) {
- pr_err("%s: failed to get resource, ret %d\n", clk_np->name,
+ pr_err("%pOFn: failed to get resource, ret %d\n", clk_np,
ret);
return;
}
prop = PALMAS_EXT_CONTROL_NSLEEP;
break;
default:
- dev_warn(&pdev->dev, "%s: Invalid ext control option: %u\n",
- node->name, prop);
+ dev_warn(&pdev->dev, "%pOFn: Invalid ext control option: %u\n",
+ node, prop);
prop = 0;
break;
}
rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
if (rc) {
- pr_err("%s: Couldn't register clk provider for node %s: %d\n",
- __func__, np->name, rc);
+ pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
+ __func__, np, rc);
return;
}
}
rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data);
if (rc) {
- pr_err("%s: Couldn't register clk provider for node %s: %d\n",
- __func__, np->name, rc);
+ pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
+ __func__, np, rc);
goto err_cell;
}
is_old_ls1021a = true;
}
if (!clockgen.regs) {
- pr_err("%s(): %s: of_iomap() failed\n", __func__, np->name);
+ pr_err("%s(): %pOFn: of_iomap() failed\n", __func__, np);
return;
}
ret = of_clk_add_provider(np, clockgen_clk_get, &clockgen);
if (ret) {
- pr_err("%s: Couldn't register clk provider for node %s: %d\n",
- __func__, np->name, ret);
+ pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
+ __func__, np, ret);
}
return;
count = handle->clk_ops->count_get(handle);
if (count < 0) {
- dev_err(dev, "%s: invalid clock output count\n", np->name);
+ dev_err(dev, "%pOFn: invalid clock output count\n", np);
return -EINVAL;
}
count = of_property_count_strings(np, "clock-output-names");
if (count < 0) {
- dev_err(dev, "%s: invalid clock output count\n", np->name);
+ dev_err(dev, "%pOFn: invalid clock output count\n", np);
return -EINVAL;
}
if (of_property_read_string_index(np, "clock-output-names",
idx, &name)) {
- dev_err(dev, "invalid clock name @ %s\n", np->name);
+ dev_err(dev, "invalid clock name @ %pOFn\n", np);
return -EINVAL;
}
if (of_property_read_u32_index(np, "clock-indices",
idx, &val)) {
- dev_err(dev, "invalid clock index @ %s\n", np->name);
+ dev_err(dev, "invalid clock index @ %pOFn\n", np);
return -EINVAL;
}
/* per clkout properties */
for_each_child_of_node(np, child) {
if (of_property_read_u32(child, "reg", &num)) {
- dev_err(&client->dev, "missing reg property of %s\n",
- child->name);
+ dev_err(&client->dev, "missing reg property of %pOFn\n",
+ child);
goto put_child;
}
base = of_iomap(np, 0);
if (!base) {
- pr_err("%s: unable to map resource\n", np->name);
+ pr_err("%pOFn: unable to map resource\n", np);
return;
}
/* get RCC base @ from DT */
base = of_iomap(np, 0);
if (!base) {
- pr_err("%s: unable to map resource", np->name);
+ pr_err("%pOFn: unable to map resource", np);
goto err_free_clks;
}
base = of_iomap(np, 0);
if (!base) {
- pr_err("%s: unable to map resource", np->name);
+ pr_err("%pOFn: unable to map resource", np);
of_node_put(np);
return;
}
const char *parent = of_clk_get_parent_name(np, 0);
if (!base)
- panic("%s: invalid address\n", np->name);
+ panic("%pOFn: invalid address\n", np);
if (readl(base + CPUCLK_DIV) & DIV_BYPASS)
- panic("%s: unsupported cpuclk setup\n", np->name);
+ panic("%pOFn: unsupported cpuclk setup\n", np);
if (readl(base + SYSCLK_DIV) & DIV_BYPASS)
- panic("%s: unsupported sysclk setup\n", np->name);
+ panic("%pOFn: unsupported sysclk setup\n", np);
writel(0x100, base + CPUCLK_DIV); /* disable frequency ramping */
pp[3] = clk_register_fixed_factor(NULL, "sdio_clk", "cd6", 0, 1, 2);
if (IS_ERR(pp[0]) || IS_ERR(pp[1]) || IS_ERR(pp[2]) || IS_ERR(pp[3]))
- panic("%s: clk registration failed\n", np->name);
+ panic("%pOFn: clk registration failed\n", np);
if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data))
- panic("%s: clk provider registration failed\n", np->name);
+ panic("%pOFn: clk provider registration failed\n", np);
}
CLK_OF_DECLARE(tango4_clkgen, "sigma,tango4-clkgen", tango4_clkgen_setup);
return;
}
- pr_err("%s: error registering clk %s\n", __func__, node->name);
+ pr_err("%s: error registering clk %pOFn\n", __func__, node);
unmap_domain:
iounmap(data->domain_base);
}
out:
- pr_err("%s: error initializing pll %s\n", __func__, node->name);
+ pr_err("%s: error initializing pll %pOFn\n", __func__, node);
kfree(pll_data);
}
num_parents = of_clk_get_parent_count(np);
if (num_parents < 1) {
- pr_err("%s: no parent found for %s DIV6 clock\n",
- __func__, np->name);
+ pr_err("%s: no parent found for %pOFn DIV6 clock\n",
+ __func__, np);
return;
}
reg = of_iomap(np, 0);
if (reg == NULL) {
- pr_err("%s: failed to map %s DIV6 clock register\n",
- __func__, np->name);
+ pr_err("%s: failed to map %pOFn DIV6 clock register\n",
+ __func__, np);
goto error;
}
clk = cpg_div6_register(clk_name, num_parents, parent_names, reg, NULL);
if (IS_ERR(clk)) {
- pr_err("%s: failed to register %s DIV6 clock (%ld)\n",
- __func__, np->name, PTR_ERR(clk));
+ pr_err("%s: failed to register %pOFn DIV6 clock (%ld)\n",
+ __func__, np, PTR_ERR(clk));
goto error;
}
clk = clk_register_divider(NULL, np->name, parent_name, 0,
smu_base + reg[0], reg[1], 8, 0, &lock);
of_clk_add_provider(np, of_clk_src_simple_get, clk);
- clk_register_clkdev(clk, np->name, NULL);
- pr_debug("## %s %s %p\n", __func__, np->name, clk);
+ clk_register_clkdev(clk, np->full_name, NULL);
+ pr_debug("## %s %pOFn %p\n", __func__, np, clk);
}
CLK_OF_DECLARE(emev2_smu_clkdiv, "renesas,emev2-smu-clkdiv",
emev2_smu_clkdiv_init);
clk = clk_register_gate(NULL, np->name, parent_name, 0,
smu_base + reg[0], reg[1], 0, &lock);
of_clk_add_provider(np, of_clk_src_simple_get, clk);
- clk_register_clkdev(clk, np->name, NULL);
- pr_debug("## %s %s %p\n", __func__, np->name, clk);
+ clk_register_clkdev(clk, np->full_name, NULL);
+ pr_debug("## %s %pOFn %p\n", __func__, np, clk);
}
CLK_OF_DECLARE(emev2_smu_gclk, "renesas,emev2-smu-gclk", emev2_smu_gclk_init);
break;
if (clkidx >= MSTP_MAX_CLOCKS) {
- pr_err("%s: invalid clock %s %s index %u\n",
- __func__, np->name, name, clkidx);
+ pr_err("%s: invalid clock %pOFn %s index %u\n",
+ __func__, np, name, clkidx);
continue;
}
*/
clk_register_clkdev(clks[clkidx], name, NULL);
} else {
- pr_err("%s: failed to register %s %s clock (%ld)\n",
- __func__, np->name, name, PTR_ERR(clks[clkidx]));
+ pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
+ __func__, np, name, PTR_ERR(clks[clkidx]));
}
}
clk = r8a73a4_cpg_register_clock(np, cpg, name);
if (IS_ERR(clk))
- pr_err("%s: failed to register %s %s clock (%ld)\n",
- __func__, np->name, name, PTR_ERR(clk));
+ pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
+ __func__, np, name, PTR_ERR(clk));
else
cpg->data.clks[i] = clk;
}
clk = r8a7740_cpg_register_clock(np, cpg, name);
if (IS_ERR(clk))
- pr_err("%s: failed to register %s %s clock (%ld)\n",
- __func__, np->name, name, PTR_ERR(clk));
+ pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
+ __func__, np, name, PTR_ERR(clk));
else
cpg->data.clks[i] = clk;
}
clk = r8a7778_cpg_register_clock(np, cpg, name);
if (IS_ERR(clk))
- pr_err("%s: failed to register %s %s clock (%ld)\n",
- __func__, np->name, name, PTR_ERR(clk));
+ pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
+ __func__, np, name, PTR_ERR(clk));
else
cpg->data.clks[i] = clk;
}
clk = r8a7779_cpg_register_clock(np, cpg, config,
plla_mult, name);
if (IS_ERR(clk))
- pr_err("%s: failed to register %s %s clock (%ld)\n",
- __func__, np->name, name, PTR_ERR(clk));
+ pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
+ __func__, np, name, PTR_ERR(clk));
else
cpg->data.clks[i] = clk;
}
clk = rcar_gen2_cpg_register_clock(np, cpg, config, name);
if (IS_ERR(clk))
- pr_err("%s: failed to register %s %s clock (%ld)\n",
- __func__, np->name, name, PTR_ERR(clk));
+ pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
+ __func__, np, name, PTR_ERR(clk));
else
cpg->data.clks[i] = clk;
}
clk = rz_cpg_register_clock(np, cpg, name);
if (IS_ERR(clk))
- pr_err("%s: failed to register %s %s clock (%ld)\n",
- __func__, np->name, name, PTR_ERR(clk));
+ pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
+ __func__, np, name, PTR_ERR(clk));
else
cpg->data.clks[i] = clk;
}
clk = sh73a0_cpg_register_clock(np, cpg, name);
if (IS_ERR(clk))
- pr_err("%s: failed to register %s %s clock (%ld)\n",
- __func__, np->name, name, PTR_ERR(clk));
+ pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
+ __func__, np, name, PTR_ERR(clk));
else
cpg->data.clks[i] = clk;
}
if (!clk_parent_name)
return;
- pll_name = kasprintf(GFP_KERNEL, "%s.pll", np->name);
+ pll_name = kasprintf(GFP_KERNEL, "%pOFn.pll", np);
if (!pll_name)
return;
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
if (IS_ERR(reg)) {
- pr_err("Could not get registers for mod0-clk: %s\n",
- node->name);
+ pr_err("Could not get registers for mod0-clk: %pOFn\n",
+ node);
return;
}
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
if (IS_ERR(reg)) {
- pr_err("Couldn't map the %s clock registers\n", node->name);
+ pr_err("Couldn't map the %pOFn clock registers\n", node);
return;
}
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
if (IS_ERR(reg)) {
- pr_err("Could not get registers for a80-pll4-clk: %s\n",
- node->name);
+ pr_err("Could not get registers for a80-pll4-clk: %pOFn\n",
+ node);
return;
}
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
if (IS_ERR(reg)) {
- pr_err("Could not get registers for a80-gt-clk: %s\n",
- node->name);
+ pr_err("Could not get registers for a80-gt-clk: %pOFn\n",
+ node);
return;
}
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
if (IS_ERR(reg)) {
- pr_err("Could not get registers for a80-ahb-clk: %s\n",
- node->name);
+ pr_err("Could not get registers for a80-ahb-clk: %pOFn\n",
+ node);
return;
}
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
if (IS_ERR(reg)) {
- pr_err("Could not get registers for a80-apb0-clk: %s\n",
- node->name);
+ pr_err("Could not get registers for a80-apb0-clk: %pOFn\n",
+ node);
return;
}
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
if (IS_ERR(reg)) {
- pr_err("Could not get registers for a80-apb1-clk: %s\n",
- node->name);
+ pr_err("Could not get registers for a80-apb1-clk: %pOFn\n",
+ node);
return;
}
reg = of_iomap(node, 0);
if (!reg) {
- pr_err("Could not get registers for factors-clk: %s\n",
- node->name);
+ pr_err("Could not get registers for factors-clk: %pOFn\n",
+ node);
return NULL;
}
clk = of_clk_get(node, 0);
if (IS_ERR(clk)) {
- pr_debug("clk-ref for %s not ready, retry\n",
- node->name);
+ pr_debug("clk-ref for %pOFn not ready, retry\n",
+ node);
if (!ti_clk_retry_init(node, hw, omap_clk_register_apll))
return;
clk = of_clk_get(node, 1);
if (IS_ERR(clk)) {
- pr_debug("clk-bypass for %s not ready, retry\n",
- node->name);
+ pr_debug("clk-bypass for %pOFn not ready, retry\n",
+ node);
if (!ti_clk_retry_init(node, hw, omap_clk_register_apll))
return;
init->num_parents = of_clk_get_parent_count(node);
if (init->num_parents < 1) {
- pr_err("dra7 apll %s must have parent(s)\n", node->name);
+ pr_err("dra7 apll %pOFn must have parent(s)\n", node);
goto cleanup;
}
init->num_parents = of_clk_get_parent_count(node);
if (init->num_parents != 1) {
- pr_err("%s must have one parent\n", node->name);
+ pr_err("%pOFn must have one parent\n", node);
goto cleanup;
}
init->parent_names = &parent_name;
if (of_property_read_u32(node, "ti,clock-frequency", &val)) {
- pr_err("%s missing clock-frequency\n", node->name);
+ pr_err("%pOFn missing clock-frequency\n", node);
goto cleanup;
}
clk_hw->fixed_rate = val;
if (of_property_read_u32(node, "ti,bit-shift", &val)) {
- pr_err("%s missing bit-shift\n", node->name);
+ pr_err("%pOFn missing bit-shift\n", node);
goto cleanup;
}
ad->autoidle_mask = 0x3 << val;
if (of_property_read_u32(node, "ti,idlest-shift", &val)) {
- pr_err("%s missing idlest-shift\n", node->name);
+ pr_err("%pOFn missing idlest-shift\n", node);
goto cleanup;
}
init.num_parents = of_clk_get_parent_count(node);
if (init.num_parents != 1) {
- pr_err("%s: atl clock %s must have 1 parent\n", __func__,
- node->name);
+ pr_err("%s: atl clock %pOFn must have 1 parent\n", __func__,
+ node);
goto cleanup;
}
{
struct clk_init_item *retry;
- pr_debug("%s: adding to retry list...\n", node->name);
+ pr_debug("%pOFn: adding to retry list...\n", node);
retry = kzalloc(sizeof(*retry), GFP_KERNEL);
if (!retry)
return -ENOMEM;
}
if (i == CLK_MAX_MEMMAPS) {
- pr_err("clk-provider not found for %s!\n", node->name);
+ pr_err("clk-provider not found for %pOFn!\n", node);
return -ENOENT;
}
reg->index = i;
if (of_property_read_u32_index(node, "reg", index, &val)) {
- pr_err("%s must have reg[%d]!\n", node->name, index);
+ pr_err("%pOFn must have reg[%d]!\n", node, index);
return -EINVAL;
}
/* get clocks for this parent */
clocks = of_get_child_by_name(parent, "clocks");
if (!clocks) {
- pr_err("%s missing 'clocks' child node.\n", parent->name);
+ pr_err("%pOFn missing 'clocks' child node.\n", parent);
return -EINVAL;
}
while (!list_empty(&retry_list) && retries) {
list_for_each_entry_safe(retry, tmp, &retry_list, link) {
- pr_debug("retry-init: %s\n", retry->node->name);
+ pr_debug("retry-init: %pOFn\n", retry->node);
retry->func(retry->user, retry->node);
list_del(&retry->link);
kfree(retry);
struct omap_clkctrl_clk *clkctrl_clk;
int ret = 0;
- init.name = kasprintf(GFP_KERNEL, "%s:%s:%04x:%d", node->parent->name,
- node->name, offset, bit);
+ init.name = kasprintf(GFP_KERNEL, "%pOFn:%pOFn:%04x:%d", node->parent,
+ node, offset, bit);
clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
if (!init.name || !clkctrl_clk) {
ret = -ENOMEM;
provider->base = of_iomap(node, 0);
- provider->clkdm_name = kmalloc(strlen(node->parent->name) + 3,
- GFP_KERNEL);
+ provider->clkdm_name = kasprintf(GFP_KERNEL, "%pOFnxxx", node->parent);
if (!provider->clkdm_name) {
kfree(provider);
return;
* Create default clkdm name, replace _cm from end of parent node
* name with _clkdm
*/
- strcpy(provider->clkdm_name, node->parent->name);
- provider->clkdm_name[strlen(provider->clkdm_name) - 2] = 0;
+ provider->clkdm_name[strlen(provider->clkdm_name) - 5] = 0;
strcat(provider->clkdm_name, "clkdm");
INIT_LIST_HEAD(&provider->clocks);
init.flags = 0;
if (reg_data->flags & CLKF_SET_RATE_PARENT)
init.flags |= CLK_SET_RATE_PARENT;
- init.name = kasprintf(GFP_KERNEL, "%s:%s:%04x:%d",
- node->parent->name, node->name,
+ init.name = kasprintf(GFP_KERNEL, "%pOFn:%pOFn:%04x:%d",
+ node->parent, node,
reg_data->offset, 0);
clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
if (!init.name || !clkctrl_clk)
comp = _lookup_component(cclk->comp_nodes[i]);
if (!comp) {
- pr_debug("component %s not ready for %s, retry\n",
- cclk->comp_nodes[i]->name, node->name);
+ pr_debug("component %s not ready for %pOFn, retry\n",
+ cclk->comp_nodes[i]->name, node);
if (!ti_clk_retry_init(node, hw,
_register_composite))
return;
goto cleanup;
}
if (cclk->comp_clks[comp->type] != NULL) {
- pr_err("duplicate component types for %s (%s)!\n",
- node->name, component_clk_types[comp->type]);
+ pr_err("duplicate component types for %pOFn (%s)!\n",
+ node, component_clk_types[comp->type]);
goto cleanup;
}
}
if (!num_parents) {
- pr_err("%s: no parents found for %s!\n", __func__, node->name);
+ pr_err("%s: no parents found for %pOFn!\n", __func__, node);
goto cleanup;
}
num_clks = of_clk_get_parent_count(node);
if (!num_clks) {
- pr_err("composite clk %s must have component(s)\n", node->name);
+ pr_err("composite clk %pOFn must have component(s)\n", node);
return;
}
num_parents = of_clk_get_parent_count(node);
if (!num_parents) {
- pr_err("component-clock %s must have parent(s)\n", node->name);
+ pr_err("component-clock %pOFn must have parent(s)\n", node);
return -EINVAL;
}
}
if (!valid_div) {
- pr_err("no valid dividers for %s table\n", node->name);
+ pr_err("no valid dividers for %pOFn table\n", node);
return ERR_PTR(-EINVAL);
}
min_div = 1;
if (of_property_read_u32(node, "ti,max-div", &max_div)) {
- pr_err("no max-div for %s!\n", node->name);
+ pr_err("no max-div for %pOFn!\n", node);
return -EINVAL;
}
clk = of_clk_get(node, 0);
if (IS_ERR(clk)) {
- pr_debug("clk-ref missing for %s, retry later\n",
- node->name);
+ pr_debug("clk-ref missing for %pOFn, retry later\n",
+ node);
if (!ti_clk_retry_init(node, hw, _register_dpll))
return;
clk = of_clk_get(node, 1);
if (IS_ERR(clk)) {
- pr_debug("clk-bypass missing for %s, retry later\n",
- node->name);
+ pr_debug("clk-bypass missing for %pOFn, retry later\n",
+ node);
if (!ti_clk_retry_init(node, hw, _register_dpll))
return;
parent_name = of_clk_get_parent_name(node, 0);
if (!parent_name) {
- pr_err("%s must have parent\n", node->name);
+ pr_err("%pOFn must have parent\n", node);
return;
}
init->num_parents = of_clk_get_parent_count(node);
if (!init->num_parents) {
- pr_err("%s must have parent(s)\n", node->name);
+ pr_err("%pOFn must have parent(s)\n", node);
goto cleanup;
}
init->num_parents = of_clk_get_parent_count(node);
if (init->num_parents != 2) {
- pr_err("%s must have two parents\n", node->name);
+ pr_err("%pOFn must have two parents\n", node);
goto free;
}
fd->clk_ref = of_clk_get(node, 0);
if (IS_ERR(fd->clk_ref)) {
- pr_err("%s could not get clk_ref\n", node->name);
+ pr_err("%pOFn could not get clk_ref\n", node);
goto free;
}
fd->clk_bypass = of_clk_get(node, 1);
if (IS_ERR(fd->clk_bypass)) {
- pr_err("%s could not get clk_bypass\n", node->name);
+ pr_err("%pOFn could not get clk_bypass\n", node);
goto free;
}
fd->base = of_iomap(node, 0);
if (!fd->base) {
- pr_err("%s could not get IO base\n", node->name);
+ pr_err("%pOFn could not get IO base\n", node);
goto free;
}
u32 flags = 0;
if (of_property_read_u32(node, "ti,clock-div", &div)) {
- pr_err("%s must have a clock-div property\n", node->name);
+ pr_err("%pOFn must have a clock-div property\n", node);
return;
}
if (of_property_read_u32(node, "ti,clock-mult", &mult)) {
- pr_err("%s must have a clock-mult property\n", node->name);
+ pr_err("%pOFn must have a clock-mult property\n", node);
return;
}
}
if (of_clk_get_parent_count(node) != 1) {
- pr_err("%s must have 1 parent\n", node->name);
+ pr_err("%pOFn must have 1 parent\n", node);
return;
}
parent_name = of_clk_get_parent_name(node, 0);
if (!parent_name) {
- pr_err("%s must have a parent\n", node->name);
+ pr_err("%pOFn must have a parent\n", node);
return;
}
num_parents = of_clk_get_parent_count(node);
if (num_parents < 2) {
- pr_err("mux-clock %s must have parents\n", node->name);
+ pr_err("mux-clock %pOFn must have parents\n", node);
return;
}
parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
num_parents = of_clk_get_parent_count(node);
if (num_parents < 2) {
- pr_err("%s must have parents\n", node->name);
+ pr_err("%pOFn must have parents\n", node);
goto cleanup;
}
}
if (of_address_to_resource(np, 0, &res)) {
- pr_err("%s: failed to get resource\n", np->name);
+ pr_err("%pOFn: failed to get resource\n", np);
goto np_err;
}
if (slcr->data) {
zynq_clkc_base = (__force void __iomem *)slcr->data + res.start;
} else {
- pr_err("%s: Unable to get I/O memory\n", np->name);
+ pr_err("%pOFn: Unable to get I/O memory\n", np);
of_node_put(slcr);
goto np_err;
}