drm/amd/display: fix dprefclk and ss percentage reading on RN

[Why]
Before was using HW counter value to determine the dprefclk. Which
take into account ss, but has large variation, not good enough for
generating audio dto. Also, the bios parser code to get the ss
percentage was not working.

[How]
After this change, dprefclk is hard coded, same as on RV. We don't
expect this to change on Renoir. Modified bios parser code to get
the right ss percentage.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 2a74be731faa697781dc2e38908a17a605d5b451..2f1c9584ac32d5c03cd999a50fdf69cc52dffc4b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -834,6 +834,7 @@ static enum bp_result bios_parser_get_spread_spectrum_info(
                case 1:
                        return get_ss_info_v4_1(bp, signal, index, ss_info);
                case 2:
+               case 3:
                        return get_ss_info_v4_2(bp, signal, index, ss_info);
                default:
                        break;

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 89ed230cdb2676c6ecb4900f3b0a06f20753053e..307c8540e36fd21d2c1f51742b5c47dff58cf35b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -675,7 +675,6 @@ void rn_clk_mgr_construct(
 {
        struct dc_debug_options *debug = &ctx->dc->debug;
        struct dpm_clocks clock_table = { 0 };
-       struct clk_state_registers_and_bypass s = { 0 };
 
        clk_mgr->base.ctx = ctx;
        clk_mgr->base.funcs = &dcn21_funcs;
@@ -695,7 +694,6 @@ void rn_clk_mgr_construct(
        if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
                dcn21_funcs.update_clocks = dcn2_update_clocks_fpga;
                clk_mgr->base.dentist_vco_freq_khz = 3600000;
-               clk_mgr->base.dprefclk_khz = 600000;
        } else {
                struct clk_log_info log_info = {0};
 
@@ -706,24 +704,16 @@ void rn_clk_mgr_construct(
                if (clk_mgr->base.dentist_vco_freq_khz == 0)
                        clk_mgr->base.dentist_vco_freq_khz = 3600000;
 
-               rn_dump_clk_registers(&s, &clk_mgr->base, &log_info);
-               /* Convert dprefclk units from MHz to KHz */
-               /* Value already divided by 10, some resolution lost */
-               clk_mgr->base.dprefclk_khz = s.dprefclk * 1000;
-
-               /* in case we don't get a value from the register, use default */
-               if (clk_mgr->base.dprefclk_khz == 0) {
-                       ASSERT(clk_mgr->base.dprefclk_khz == 600000);
-                       clk_mgr->base.dprefclk_khz = 600000;
-               }
-
                if (ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) {
                        rn_bw_params.wm_table = lpddr4_wm_table;
                } else {
                        rn_bw_params.wm_table = ddr4_wm_table;
                }
+               /* Saved clocks configured at boot for debug purposes */
+               rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
        }
 
+       clk_mgr->base.dprefclk_khz = 600000;
        dce_clock_read_ss_info(clk_mgr);
 
 

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index 4aa09fe954c56e8e9ba9c3864026f98f6ddeb71c..ac530c057ddda6584c5dce8e899e137fbadc5e1e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -191,6 +191,7 @@ struct clk_mgr {
        bool psr_allow_active_cache;
        int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes
        int dentist_vco_freq_khz;
+       struct clk_state_registers_and_bypass boot_snapshot;
        struct clk_bw_params *bw_params;
 };