]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
drm/meson: fix G12A HDMI PLL settings for 4K60 1000/1001 variations
authorNeil Armstrong <narmstrong@baylibre.com>
Wed, 5 Jun 2019 12:53:20 +0000 (14:53 +0200)
committerNeil Armstrong <narmstrong@baylibre.com>
Fri, 7 Jun 2019 08:03:57 +0000 (10:03 +0200)
The Amlogic G12A HDMI PLL needs some specific settings to lock with
different fractional values for the 5,4GHz mode.

Handle the 1000/1001 variation fractional case here to avoid having
the PLL in an non lockable state.

Fixes: 202b9808f8ed ("drm/meson: Add G12A Video Clock setup")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190605125320.8708-1-narmstrong@baylibre.com
drivers/gpu/drm/meson/meson_vclk.c

index 58b4af5fbb6d16280b74bd11723b3e5a6bd52d05..26732f038d19f7838ee24dabd21b00d9dec7068e 100644 (file)
@@ -503,8 +503,17 @@ void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m,
 
                /* G12A HDMI PLL Needs specific parameters for 5.4GHz */
                if (m >= 0xf7) {
-                       regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0xea68dc00);
-                       regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x65771290);
+                       if (frac < 0x10000) {
+                               regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4,
+                                                       0x6a685c00);
+                               regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5,
+                                                       0x11551293);
+                       } else {
+                               regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4,
+                                                       0xea68dc00);
+                               regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5,
+                                                       0x65771290);
+                       }
                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000);
                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x55540000);
                } else {