drm/amd/display: fixing register includes

Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 2d3a41f744af171aa9ec855ff1eec5d01173509b..589332019a8300b42f253c687665450b8114c7bf 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -131,8 +131,6 @@
        HWSEQ_PHYPLL_REG_LIST(CRTC)
 
 #define HWSEQ_DCN_REG_LIST()\
-       HWSEQ_PIXEL_RATE_REG_LIST(OTG), \
-       HWSEQ_PHYPLL_REG_LIST(OTG), \
        SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 0), \
        SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 1), \
        SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 2), \
@@ -182,22 +180,6 @@
        SR(DCHUBBUB_TEST_DEBUG_INDEX), \
        SR(DCHUBBUB_TEST_DEBUG_DATA), \
        SR(DC_IP_REQUEST_CNTL), \
-       SR(DOMAIN0_PG_CONFIG), \
-       SR(DOMAIN1_PG_CONFIG), \
-       SR(DOMAIN2_PG_CONFIG), \
-       SR(DOMAIN3_PG_CONFIG), \
-       SR(DOMAIN4_PG_CONFIG), \
-       SR(DOMAIN5_PG_CONFIG), \
-       SR(DOMAIN6_PG_CONFIG), \
-       SR(DOMAIN7_PG_CONFIG), \
-       SR(DOMAIN0_PG_STATUS), \
-       SR(DOMAIN1_PG_STATUS), \
-       SR(DOMAIN2_PG_STATUS), \
-       SR(DOMAIN3_PG_STATUS), \
-       SR(DOMAIN4_PG_STATUS), \
-       SR(DOMAIN5_PG_STATUS), \
-       SR(DOMAIN6_PG_STATUS), \
-       SR(DOMAIN7_PG_STATUS), \
        SR(DIO_MEM_PWR_CTRL), \
        SR(DCCG_GATE_DISABLE_CNTL), \
        SR(DCCG_GATE_DISABLE_CNTL2), \
@@ -223,13 +205,30 @@
 
 #define HWSEQ_DCN1_REG_LIST()\
        HWSEQ_DCN_REG_LIST(), \
+       HWSEQ_PIXEL_RATE_REG_LIST(OTG), \
+       HWSEQ_PHYPLL_REG_LIST(OTG), \
        SR(DCHUBBUB_SDPIF_FB_TOP),\
        SR(DCHUBBUB_SDPIF_FB_BASE),\
        SR(DCHUBBUB_SDPIF_FB_OFFSET),\
        SR(DCHUBBUB_SDPIF_AGP_BASE),\
        SR(DCHUBBUB_SDPIF_AGP_BOT),\
-       SR(DCHUBBUB_SDPIF_AGP_TOP)
-
+       SR(DCHUBBUB_SDPIF_AGP_TOP),\
+       SR(DOMAIN0_PG_CONFIG), \
+       SR(DOMAIN1_PG_CONFIG), \
+       SR(DOMAIN2_PG_CONFIG), \
+       SR(DOMAIN3_PG_CONFIG), \
+       SR(DOMAIN4_PG_CONFIG), \
+       SR(DOMAIN5_PG_CONFIG), \
+       SR(DOMAIN6_PG_CONFIG), \
+       SR(DOMAIN7_PG_CONFIG), \
+       SR(DOMAIN0_PG_STATUS), \
+       SR(DOMAIN1_PG_STATUS), \
+       SR(DOMAIN2_PG_STATUS), \
+       SR(DOMAIN3_PG_STATUS), \
+       SR(DOMAIN4_PG_STATUS), \
+       SR(DOMAIN5_PG_STATUS), \
+       SR(DOMAIN6_PG_STATUS), \
+       SR(DOMAIN7_PG_STATUS)
 
 struct dce_hwseq_registers {
        uint32_t DCFE_CLOCK_CONTROL[6];
@@ -417,30 +416,6 @@ struct dce_hwseq_registers {
        HWS_SF(OPP_PIPE0_, OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh),\
        HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
        HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
-       HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
-       HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
-       HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
-       HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
-       HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
-       HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
-       HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
-       HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
-       HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
-       HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
-       HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
-       HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
-       HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
-       HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
-       HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
-       HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
-       HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
-       HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
-       HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
-       HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
-       HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
-       HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
-       HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
-       HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
        HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \
        HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \
        HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \
@@ -468,7 +443,31 @@ struct dce_hwseq_registers {
        HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\
        HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\
        HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\
-       HWS_SF(, MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh)
+       HWS_SF(, MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh),\
+       HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
+       HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
+       HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
+       HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
+       HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
+       HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
+       HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
+       HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
+       HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
+       HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
+       HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
+       HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
+       HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
+       HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
+       HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
+       HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
+       HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
+       HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
+       HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
+       HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
+       HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
+       HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
+       HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
+       HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh)
 
 #define HWSEQ_REG_FIELD_LIST(type) \
        type DCFE_CLOCK_ENABLE; \

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
index aefd3e7bd7eb22ba295f7298176e11eb73fde463..0b7d4faff82fa081bc6bb03de0f76cd0199b430b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
@@ -120,6 +120,8 @@
        SR(DCHUBBUB_SDPIF_FB_BASE),\
        SR(DCHUBBUB_SDPIF_FB_OFFSET)
 
+
+
 struct dcn_mi_registers {
        uint32_t DCHUBP_CNTL;
        uint32_t HUBPREQ_DEBUG_DB;