]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
drm/amdgpu: Add DC feature mask to disable fractional pwm
authorLeo Li <sunpeng.li@amd.com>
Mon, 21 Oct 2019 18:58:47 +0000 (14:58 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 25 Oct 2019 20:50:10 +0000 (16:50 -0400)
[Why]

Some LED panel drivers might not like fractional PWM. In such cases,
backlight flickering may be observed.

[How]

Add a DC feature mask to disable fractional PWM, and associate it with
the preexisting dc_config flag.

The flag is only plumbed through the dmcu firmware, so plumb it through
the driver path as well.

To disable, add the following to the linux cmdline:
amdgpu.dcfeaturemask=0x4

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204957
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Anthony Koo <anthony.koo@amd.com>
Tested-by: Lukáš Krejčí <lskrejci@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
drivers/gpu/drm/amd/include/amd_shared.h

index 854d2caf18dd1011279ccd383898227fa8e9e414..620abe29ef08451f75596374f06afbe8c262dcbe 100644 (file)
@@ -728,6 +728,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
        if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
                init_data.flags.multi_mon_pp_mclk_switch = true;
 
+       if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
+               init_data.flags.disable_fractional_pwm = true;
+
        init_data.flags.power_down_display_on_boot = true;
 
 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
index d759fdca7fdbafe2c222c2e5a0c5fd753981773e..b8a3fc505c9b6e1a881209bd9569a8e262b92a19 100644 (file)
@@ -404,6 +404,10 @@ static bool dce_abm_init_backlight(struct abm *abm)
        /* Enable the backlight output */
        REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1);
 
+       /* Disable fractional pwm if configured */
+       REG_UPDATE(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN,
+                  abm->ctx->dc->config.disable_fractional_pwm ? 0 : 1);
+
        /* Unlock group 2 backlight registers */
        REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
                        BL_PWM_GRP1_REG_LOCK, 0);
index 8340ec0ab792631786deaba69c8ac4f23d8306a2..dc7eb28f029672c2de42ffdca58645da575b378e 100644 (file)
@@ -143,6 +143,7 @@ enum PP_FEATURE_MASK {
 enum DC_FEATURE_MASK {
        DC_FBC_MASK = 0x1,
        DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2,
+       DC_DISABLE_FRACTIONAL_PWM_MASK = 0x4,
        DC_PSR_MASK = 0x8,
 };