]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
dt-bindings: ARM: Mediatek: Document bindings for MT2712
authorweiyi.lu@mediatek.com <weiyi.lu@mediatek.com>
Mon, 23 Oct 2017 04:10:32 +0000 (12:10 +0800)
committerStephen Boyd <sboyd@codeaurora.org>
Thu, 2 Nov 2017 07:57:15 +0000 (00:57 -0700)
This patch adds the binding documentation for apmixedsys, bdpsys,
imgsys, imgsys, infracfg, mcucfg, mfgcfg, mmsys, pericfg, topckgen,
vdecsys and vencsys for Mediatek MT2712.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
12 files changed:
Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt [new file with mode: 0644]
Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt [new file with mode: 0644]
Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt [new file with mode: 0644]
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt

index cd977db7630c50a6e118e60edd96256efa138ac9..19fc116346d6bd41c629406299b79c4f4235184d 100644 (file)
@@ -7,6 +7,7 @@ Required Properties:
 
 - compatible: Should be one of:
        - "mediatek,mt2701-apmixedsys"
+       - "mediatek,mt2712-apmixedsys", "syscon"
        - "mediatek,mt6797-apmixedsys"
        - "mediatek,mt8135-apmixedsys"
        - "mediatek,mt8173-apmixedsys"
index 4137196dd686fc0648d3a785c2b3462ac47c11cd..4010e37c53a0218554edfb5885262a168ba73108 100644 (file)
@@ -7,6 +7,7 @@ Required Properties:
 
 - compatible: Should be:
        - "mediatek,mt2701-bdpsys", "syscon"
+       - "mediatek,mt2712-bdpsys", "syscon"
 - #clock-cells: Must be 1
 
 The bdpsys controller uses the common clk binding from
index 047b11ae5f45c0a7e020a231a4e87ce656b3842e..868bd51a98befcb5d901bf67995525e9dceb8173 100644 (file)
@@ -7,6 +7,7 @@ Required Properties:
 
 - compatible: Should be one of:
        - "mediatek,mt2701-imgsys", "syscon"
+       - "mediatek,mt2712-imgsys", "syscon"
        - "mediatek,mt6797-imgsys", "syscon"
        - "mediatek,mt8173-imgsys", "syscon"
 - #clock-cells: Must be 1
index 58d58e2006b83324502d3d39739ab6537552649b..a3430cd96d0f9f8839ff95f95a45ed1dc0b11b52 100644 (file)
@@ -8,6 +8,7 @@ Required Properties:
 
 - compatible: Should be one of:
        - "mediatek,mt2701-infracfg", "syscon"
+       - "mediatek,mt2712-infracfg", "syscon"
        - "mediatek,mt6797-infracfg", "syscon"
        - "mediatek,mt8135-infracfg", "syscon"
        - "mediatek,mt8173-infracfg", "syscon"
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt
new file mode 100644 (file)
index 0000000..2df799c
--- /dev/null
@@ -0,0 +1,22 @@
+Mediatek jpgdecsys controller
+============================
+
+The Mediatek jpgdecsys controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be:
+       - "mediatek,mt2712-jpgdecsys", "syscon"
+- #clock-cells: Must be 1
+
+The jpgdecsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+jpgdecsys: syscon@19000000 {
+       compatible = "mediatek,mt2712-jpgdecsys", "syscon";
+       reg = <0 0x19000000 0 0x1000>;
+       #clock-cells = <1>;
+};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt
new file mode 100644 (file)
index 0000000..b8fb03f
--- /dev/null
@@ -0,0 +1,22 @@
+Mediatek mcucfg controller
+============================
+
+The Mediatek mcucfg controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be one of:
+       - "mediatek,mt2712-mcucfg", "syscon"
+- #clock-cells: Must be 1
+
+The mcucfg controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+mcucfg: syscon@10220000 {
+       compatible = "mediatek,mt2712-mcucfg", "syscon";
+       reg = <0 0x10220000 0 0x1000>;
+       #clock-cells = <1>;
+};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
new file mode 100644 (file)
index 0000000..859e67b
--- /dev/null
@@ -0,0 +1,22 @@
+Mediatek mfgcfg controller
+============================
+
+The Mediatek mfgcfg controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be one of:
+       - "mediatek,mt2712-mfgcfg", "syscon"
+- #clock-cells: Must be 1
+
+The mfgcfg controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+mfgcfg: syscon@13000000 {
+       compatible = "mediatek,mt2712-mfgcfg", "syscon";
+       reg = <0 0x13000000 0 0x1000>;
+       #clock-cells = <1>;
+};
index 70529e0b58e9a15927a552ada8106434c1627100..4eb8bbe15c01cd4828a75a9acb1d8913e231e515 100644 (file)
@@ -7,6 +7,7 @@ Required Properties:
 
 - compatible: Should be one of:
        - "mediatek,mt2701-mmsys", "syscon"
+       - "mediatek,mt2712-mmsys", "syscon"
        - "mediatek,mt6797-mmsys", "syscon"
        - "mediatek,mt8173-mmsys", "syscon"
 - #clock-cells: Must be 1
index e494366782aaf79e1a092be3dd701dd2c22b5a37..d9f092eb35505166512c21897a520cc260249814 100644 (file)
@@ -8,6 +8,7 @@ Required Properties:
 
 - compatible: Should be one of:
        - "mediatek,mt2701-pericfg", "syscon"
+       - "mediatek,mt2712-pericfg", "syscon"
        - "mediatek,mt8135-pericfg", "syscon"
        - "mediatek,mt8173-pericfg", "syscon"
 - #clock-cells: Must be 1
index ec93ecbb9f3c2fb72bf461d8d57275d8c57ac79a..2024fc909d69b6ad010204c80004ded730d591c6 100644 (file)
@@ -7,6 +7,7 @@ Required Properties:
 
 - compatible: Should be one of:
        - "mediatek,mt2701-topckgen"
+       - "mediatek,mt2712-topckgen", "syscon"
        - "mediatek,mt6797-topckgen"
        - "mediatek,mt8135-topckgen"
        - "mediatek,mt8173-topckgen"
index d150104f928a4f7c023a724a3e646eb11b49d83a..ea40d05089f8306b2b15e2b0cd304ef61b8f8602 100644 (file)
@@ -7,6 +7,7 @@ Required Properties:
 
 - compatible: Should be one of:
        - "mediatek,mt2701-vdecsys", "syscon"
+       - "mediatek,mt2712-vdecsys", "syscon"
        - "mediatek,mt6797-vdecsys", "syscon"
        - "mediatek,mt8173-vdecsys", "syscon"
 - #clock-cells: Must be 1
index 8a93be643647d429c39ba3c978e6e1a02f94d1c4..851545357e94af7f3ec4a96ac882cded0d166d7e 100644 (file)
@@ -6,6 +6,7 @@ The Mediatek vencsys controller provides various clocks to the system.
 Required Properties:
 
 - compatible: Should be one of:
+       - "mediatek,mt2712-vencsys", "syscon"
        - "mediatek,mt6797-vencsys", "syscon"
        - "mediatek,mt8173-vencsys", "syscon"
 - #clock-cells: Must be 1