]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
ARM: trusted_foundations: Support L2 cache maintenance
authorDmitry Osipenko <digetx@gmail.com>
Sun, 17 Mar 2019 22:52:04 +0000 (01:52 +0300)
committerThierry Reding <treding@nvidia.com>
Tue, 9 Apr 2019 14:36:16 +0000 (16:36 +0200)
Implement L2 cache initialization firmware callback that should be
invoked early during boot in order to set up the required outer cache
driver's callbacks and add the callback required for L2X0 maintenance.

Partially based on work done by Michał Mirosław [1].

[1] https://www.spinics.net/lists/arm-kernel/msg594765.html

Tested-by: Robert Yang <decatf@gmail.com>
Tested-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
arch/arm/firmware/trusted_foundations.c
arch/arm/include/asm/trusted_foundations.h

index 689e6565abfc4bea48e9425901387d6a096ed9d5..d7ac05103a52dd940a5ad9d1f450367d2240bd34 100644 (file)
 #include <linux/init.h>
 #include <linux/of.h>
 #include <asm/firmware.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/outercache.h>
 #include <asm/trusted_foundations.h>
 
+#define TF_CACHE_MAINT         0xfffff100
+
+#define TF_CACHE_ENABLE                1
+#define TF_CACHE_DISABLE       2
+
 #define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200
 
 #define TF_CPU_PM              0xfffffffc
@@ -67,9 +74,43 @@ static int tf_prepare_idle(void)
        return 0;
 }
 
+#ifdef CONFIG_CACHE_L2X0
+static void tf_cache_write_sec(unsigned long val, unsigned int reg)
+{
+       u32 l2x0_way_mask = 0xff;
+
+       switch (reg) {
+       case L2X0_CTRL:
+               if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_ASSOCIATIVITY_16)
+                       l2x0_way_mask = 0xffff;
+
+               if (val == L2X0_CTRL_EN)
+                       tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_ENABLE,
+                                      l2x0_saved_regs.aux_ctrl);
+               else
+                       tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_DISABLE,
+                                      l2x0_way_mask);
+               break;
+
+       default:
+               break;
+       }
+}
+
+static int tf_init_cache(void)
+{
+       outer_cache.write_sec = tf_cache_write_sec;
+
+       return 0;
+}
+#endif /* CONFIG_CACHE_L2X0 */
+
 static const struct firmware_ops trusted_foundations_ops = {
        .set_cpu_boot_addr = tf_set_cpu_boot_addr,
        .prepare_idle = tf_prepare_idle,
+#ifdef CONFIG_CACHE_L2X0
+       .l2x0_init = tf_init_cache,
+#endif
 };
 
 void register_trusted_foundations(struct trusted_foundations_platform_data *pd)
index 00748350cf72c263c862f00987ed40131451b07a..9e6a41e9215e55d9de6f24ca655e9317d279313a 100644 (file)
@@ -32,6 +32,9 @@
 #include <linux/cpu.h>
 #include <linux/smp.h>
 
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/outercache.h>
+
 struct trusted_foundations_platform_data {
        unsigned int version_major;
        unsigned int version_minor;
@@ -43,6 +46,9 @@ void register_trusted_foundations(struct trusted_foundations_platform_data *pd);
 void of_register_trusted_foundations(void);
 
 #else /* CONFIG_TRUSTED_FOUNDATIONS */
+static inline void tf_dummy_write_sec(unsigned long val, unsigned int reg)
+{
+}
 
 static inline void register_trusted_foundations(
                                   struct trusted_foundations_platform_data *pd)
@@ -53,6 +59,10 @@ static inline void register_trusted_foundations(
         */
        pr_err("No support for Trusted Foundations, continuing in degraded mode.\n");
        pr_err("Secondary processors as well as CPU PM will be disabled.\n");
+#if IS_ENABLED(CONFIG_CACHE_L2X0)
+       pr_err("L2X0 cache will be kept disabled.\n");
+       outer_cache.write_sec = tf_dummy_write_sec;
+#endif
 #if IS_ENABLED(CONFIG_SMP)
        setup_max_cpus = 0;
 #endif