ARM: dts: Configure interconnect target module for am4 sham

We can now probe devices with device tree only configuration using
ti-sysc interconnect target module driver. Let's configure the
module, but keep the legacy "ti,hwmods" peroperty to avoid new boot
time warnings. The legacy property will be removed in later patches
together with the legacy platform data.

Similar to am3, I could not find any documentation for the sysc
register on this one, but it seems to work just fine based on
"ti,sysc-omap3-sham" compatible style configuration.

Cc: Keerthy <j-keerthy@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Tested-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index d0478530515bee0e3499b3aea62e8e6cc509b9f3..4496f767c7a4ce6b7f338166444357311424a0ca 100644 (file)
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -256,13 +256,33 @@ mmc3: mmc@0 {
                        };
                };
 
-               sham: sham@53100000 {
-                       compatible = "ti,omap5-sham";
+               sham_target: target-module@53100000 {
+                       compatible = "ti,sysc-omap3-sham", "ti,sysc";
                        ti,hwmods = "sham";
-                       reg = <0x53100000 0x300>;
-                       dmas = <&edma 36 0>;
-                       dma-names = "rx";
-                       interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+                       reg = <0x53100100 0x4>,
+                             <0x53100110 0x4>,
+                             <0x53100114 0x4>;
+                       reg-names = "rev", "sysc", "syss";
+                       ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+                                        SYSC_OMAP2_AUTOIDLE)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       ti,syss-mask = <1>;
+                       /* Domains (P, C): per_pwrdm, l3_clkdm */
+                       clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x53100000 0x1000>;
+
+                       sham: sham@0 {
+                               compatible = "ti,omap5-sham";
+                               reg = <0 0x300>;
+                               dmas = <&edma 36 0>;
+                               dma-names = "rx";
+                               interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+                       };
                };
 
                aes: aes@53501000 {