]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
drm/radeon: Refuse to migrate a prime BO to VRAM. (v2)
authorChristopher James Halse Rogers <christopher.halse.rogers@canonical.com>
Mon, 3 Apr 2017 03:35:23 +0000 (13:35 +1000)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 7 Apr 2017 16:20:41 +0000 (12:20 -0400)
BOs shared via dma-buf, either imported or exported, cannot sensibly be migrated to VRAM
without breaking the dma-buf sharing. Refuse userspace requests to migrate to VRAM,
ensure such BOs are not migrated during command submission, and refuse to pin them
to VRAM.

v2: Don't pin BOs in GTT. Instead, refuse to migrate BOs to VRAM.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Christopher James Halse Rogers <christopher.halse.rogers@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/radeon_cs.c
drivers/gpu/drm/radeon/radeon_gem.c
drivers/gpu/drm/radeon/radeon_object.c

index a8442f7196d6fee625795df3cb2ae08de4155bad..df6b58c085445f9b57640d52574421f11c371e8a 100644 (file)
@@ -164,6 +164,16 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
                        p->relocs[i].allowed_domains = domain;
                }
 
+               /* Objects shared as dma-bufs cannot be moved to VRAM */
+               if (p->relocs[i].robj->prime_shared_count) {
+                       p->relocs[i].allowed_domains &= ~RADEON_GEM_DOMAIN_VRAM;
+                       if (!p->relocs[i].allowed_domains) {
+                               DRM_ERROR("BO associated with dma-buf cannot "
+                                         "be moved to VRAM\n");
+                               return -EINVAL;
+                       }
+               }
+
                p->relocs[i].tv.bo = &p->relocs[i].robj->tbo;
                p->relocs[i].tv.shared = !r->write_domain;
 
index 9b0b123ce0795175bebda639cd39bc49f8b7696c..dddb372de2b9de555ca0e0444acaf164ceed6d9d 100644 (file)
@@ -120,6 +120,10 @@ static int radeon_gem_set_domain(struct drm_gem_object *gobj,
                        return r;
                }
        }
+       if (domain == RADEON_GEM_DOMAIN_VRAM && robj->prime_shared_count) {
+               /* A BO that is associated with a dma-buf cannot be sensibly migrated to VRAM */
+               return -EINVAL;
+       }
        return 0;
 }
 
index 74b276060c205ab85fad15e59b983e76a123e349..bec2ec056de43d30f27e0c9c218036f7d324372c 100644 (file)
@@ -352,6 +352,11 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
 
                return 0;
        }
+       if (bo->prime_shared_count && domain == RADEON_GEM_DOMAIN_VRAM) {
+               /* A BO shared as a dma-buf cannot be sensibly migrated to VRAM */
+               return -EINVAL;
+       }
+
        radeon_ttm_placement_from_domain(bo, domain);
        for (i = 0; i < bo->placement.num_placement; i++) {
                /* force to pin into visible video ram */