drm/amdgpu:fix missing programing critical registers

those MC_VM registers won't be programed by VBIOS in VF
so driver is responsible to programe them.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 987b21b216f031775dc467e414e37a50eb430655..5604a53598c9ac72bed2d4b4cf0b6440cb3bb37a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -53,6 +53,15 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
                                mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),
                                (u32)(value >> 44));
 
+       if (amdgpu_sriov_vf(adev)) {
+               /* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are VF copy registers so
+               vbios post doesn't program them, for SRIOV driver need to program them */
+               WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_BASE),
+                               adev->mc.vram_start >> 24);
+               WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_TOP),
+                               adev->mc.vram_end >> 24);
+       }
+
        /* Disable AGP. */
        WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BASE), 0);
        WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_TOP), 0);

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index f1f4eac1140053bf47a821b14fbe6d764a156809..87bea71ca0c8c6a7c6cff02bc4637000c8d4e447 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -382,7 +382,9 @@ static int gmc_v9_0_late_init(void *handle)
 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
                                        struct amdgpu_mc *mc)
 {
-       u64 base = mmhub_v1_0_get_fb_location(adev);
+       u64 base = 0;
+       if (!amdgpu_sriov_vf(adev))
+               base = mmhub_v1_0_get_fb_location(adev);
        amdgpu_vram_location(adev, &adev->mc, base);
        adev->mc.gtt_base_align = 0;
        amdgpu_gtt_location(adev, mc);

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 128024aba39e3da6e64dffbfd1675fcf5e33841b..5903bb0dff15017a3492864e83c133ebdbba2037 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -67,6 +67,15 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
                                mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),
                                (u32)(value >> 44));
 
+       if (amdgpu_sriov_vf(adev)) {
+               /* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are VF copy registers so
+               vbios post doesn't program them, for SRIOV driver need to program them */
+               WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE),
+                       adev->mc.vram_start >> 24);
+               WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP),
+                       adev->mc.vram_end >> 24);
+       }
+
        /* Disable AGP. */
        WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_AGP_BASE), 0);
        WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_AGP_TOP), 0);