]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
ARC: [plat-hsdk] use actual clk driver to manage cpu clk
authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Mon, 4 Sep 2017 09:48:43 +0000 (12:48 +0300)
committerVineet Gupta <vgupta@synopsys.com>
Wed, 4 Oct 2017 03:36:49 +0000 (20:36 -0700)
With corresponding clk driver now merged upstream, switch to it.

 - core_clk now represent the PLL (vs. fixed clk before)
 - input_clk represent the clk signal src for PLL (basically xtal)

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
arch/arc/boot/dts/hsdk.dts
arch/arc/plat-hsdk/Kconfig

index daeef4ab2df91ec3ad9131013fa13ff259267b81..b922f3faf5549ddf65cf7f1974f72b260d6a2a08 100644 (file)
@@ -57,10 +57,10 @@ cpu@3 {
                };
        };
 
-       core_clk: core-clk {
+       input_clk: input-clk {
                #clock-cells = <0>;
                compatible = "fixed-clock";
-               clock-frequency = <500000000>;
+               clock-frequency = <33333333>;
        };
 
        cpu_intc: cpu-interrupt-controller {
@@ -102,6 +102,13 @@ soc {
 
                ranges = <0x00000000 0xf0000000 0x10000000>;
 
+               core_clk: core-clk@0 {
+                       compatible = "snps,hsdk-core-pll-clock";
+                       reg = <0x00 0x10>, <0x14B8 0x4>;
+                       #clock-cells = <0>;
+                       clocks = <&input_clk>;
+               };
+
                serial: serial@5000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x5000 0x100>;
index 5a6ed5afb009a160e617a5e2fd81f1be6f56fcd3..bd08de4be75e7edc4ce8875c8af7f1723f0f5b01 100644 (file)
@@ -6,4 +6,5 @@
 #
 
 menuconfig ARC_SOC_HSDK
-       bool "ARC HS Development Kit SOC"
+       bool "ARC HS Development Kit SOC"
+       select CLK_HSDK