clk: rockchip: add 65MHz and 106.5MHz rates to rk3399 plls used for HDMI

We need to add more clocks for supporting more display resolution
for HDMI.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index c109d80e7a8a96340f187a81b3699ae115928a71..e4ca8a983d12a163f0209b6d20e58196ba840397 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -100,8 +100,10 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
        RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0),
        RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
        RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),
+       RK3036_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0),
        RK3036_PLL_RATE(  96000000, 1, 64, 4, 4, 1, 0),
        RK3036_PLL_RATE(  74250000, 2, 99, 4, 4, 1, 0),
+       RK3036_PLL_RATE(  65000000, 1, 65, 6, 4, 1, 0),
        RK3036_PLL_RATE(  54000000, 1, 54, 6, 4, 1, 0),
        RK3036_PLL_RATE(  27000000, 1, 27, 6, 4, 1, 0),
        { /* sentinel */ },