ARM: dts: omap: Add reset/idle on init bindings for OMAP

On OMAP we have co-processor IPs, memory controllers,
GPIOs which control regulators and power switches to
PMIC, and SoC internal Bus IPs, some or most of which
should either not be reset or idled or both at init.
(In some cases there are erratas which prevent an IP
from being reset)
Have a way to pass this information from DT.

Update the am33xx/omap4 and omap5 dtsi files with the
new bindings for modules which either should not be
idled. reset or both. A later patch would cleanup the
same information that exists today as part of the hwmod
data files.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>

diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index 91b7049affa1ea5f5e0da13b52db79212c94ca52..808c1543b0f87f374c5d93517d8389a3b3479be9 100644 (file)
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -21,7 +21,8 @@ Required properties:
 Optional properties:
 - ti,no_idle_on_suspend: When present, it prevents the PM to idle the module
   during suspend.
-
+- ti,no-reset-on-init: When present, the module should not be reset at init
+- ti,no-idle-on-init: When present, the module should not be idled at init
 
 Example:
 

diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 7db3c81d1563f398a629603b5ae63c3e805eab11..58cf5b91a1189a0c28c4160f897b6b02dfe0aace 100644 (file)
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -674,6 +674,7 @@ wkup_m3: wkup_m3@44d00000 {
                        reg = <0x44d00000 0x4000        /* M3 UMEM */
                               0x44d80000 0x2000>;      /* M3 DMEM */
                        ti,hwmods = "wkup_m3";
+                       ti,no-reset-on-init;
                };
 
                elm: elm@48080000 {
@@ -713,6 +714,7 @@ am335x_adc: adc {
                gpmc: gpmc@50000000 {
                        compatible = "ti,am3352-gpmc";
                        ti,hwmods = "gpmc";
+                       ti,no-idle-on-init;
                        reg = <0x50000000 0x2000>;
                        interrupts = <100>;
                        gpmc,num-cs = <7>;

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 6be1f5678f1acbfdee1f02053b0333e7ab05bdfd..6ca45b0d346bec140a1ad47ac1db454bdf2e6074 100644 (file)
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -214,6 +214,7 @@ gpmc: gpmc@50000000 {
                        gpmc,num-cs = <8>;
                        gpmc,num-waitpins = <4>;
                        ti,hwmods = "gpmc";
+                       ti,no-idle-on-init;
                };
 
                uart1: serial@4806a000 {
@@ -492,6 +493,7 @@ emif1: emif@4c000000 {
                        reg = <0x4c000000 0x100>;
                        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "emif1";
+                       ti,no-idle-on-init;
                        phy-type = <1>;
                        hw-caps-read-idle-ctrl;
                        hw-caps-ll-interface;
@@ -503,6 +505,7 @@ emif2: emif@4d000000 {
                        reg = <0x4d000000 0x100>;
                        interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "emif2";
+                       ti,no-idle-on-init;
                        phy-type = <1>;
                        hw-caps-read-idle-ctrl;
                        hw-caps-ll-interface;

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 6a558cedffd6de240e02002b9857c16d937b2e90..f518ec6b6e49fc62a207f75bf5a574846942a4f9 100644 (file)
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -606,6 +606,7 @@ wdt2: wdt@4ae14000 {
                emif1: emif@4c000000 {
                        compatible      = "ti,emif-4d5";
                        ti,hwmods       = "emif1";
+                       ti,no-idle-on-init;
                        phy-type        = <2>; /* DDR PHY type: Intelli PHY */
                        reg = <0x4c000000 0x400>;
                        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
@@ -617,6 +618,7 @@ emif1: emif@4c000000 {
                emif2: emif@4d000000 {
                        compatible      = "ti,emif-4d5";
                        ti,hwmods       = "emif2";
+                       ti,no-idle-on-init;
                        phy-type        = <2>; /* DDR PHY type: Intelli PHY */
                        reg = <0x4d000000 0x400>;
                        interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;