]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
ARM: davinci: Explicitly set channel controllers' default queues
authorIdo Yariv <ido@wizery.com>
Sun, 10 Jul 2011 13:14:35 +0000 (16:14 +0300)
committerSekhar Nori <nsekhar@ti.com>
Sat, 17 Sep 2011 10:24:08 +0000 (15:54 +0530)
Davinci platforms may define a default queue for each channel
controller. If one is not defined, the default queue is set to EVENTQ_1.
However, there's no way to distinguish between an unset default queue to
one that is set to EVENTQ_0, as EVENTQ_0 = 0.

Explicitly specify the default queue for all channel controllers on all
Davinci platforms to EVENTQ_1, and don't overwrite it in the EDMA probe
function.

One exception is the DA850 board, for which EVENTQ_1 is not a valid
option for its second channel controller. Use EVENTQ_0 instead for that
channel controller.

Signed-off-by: Ido Yariv <ido@wizery.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
arch/arm/mach-davinci/devices-da8xx.c
arch/arm/mach-davinci/devices-tnetv107x.c
arch/arm/mach-davinci/dm355.c
arch/arm/mach-davinci/dm644x.c
arch/arm/mach-davinci/dm646x.c
arch/arm/mach-davinci/dma.c

index 2f7e719636f1333ce7ef3120a8393e6cd896d0dd..68def71888685b0277b1dacab25bd5bfaef1c09e 100644 (file)
@@ -136,6 +136,7 @@ static struct edma_soc_info da830_edma_cc0_info = {
        .n_cc                   = 1,
        .queue_tc_mapping       = da8xx_queue_tc_mapping,
        .queue_priority_mapping = da8xx_queue_priority_mapping,
+       .default_queue          = EVENTQ_1,
 };
 
 static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
@@ -151,6 +152,7 @@ static struct edma_soc_info da850_edma_cc_info[] = {
                .n_cc                   = 1,
                .queue_tc_mapping       = da8xx_queue_tc_mapping,
                .queue_priority_mapping = da8xx_queue_priority_mapping,
+               .default_queue          = EVENTQ_1,
        },
        {
                .n_channel              = 32,
@@ -160,6 +162,7 @@ static struct edma_soc_info da850_edma_cc_info[] = {
                .n_cc                   = 1,
                .queue_tc_mapping       = da850_queue_tc_mapping,
                .queue_priority_mapping = da850_queue_priority_mapping,
+               .default_queue          = EVENTQ_0,
        },
 };
 
index 6162cae7f868e2febb07f4c3496ff61443356bb1..29b17f7d3a5fae67089cb181813f8193ff46e05a 100644 (file)
@@ -80,6 +80,7 @@ static struct edma_soc_info edma_cc0_info = {
        .n_cc                   = 1,
        .queue_tc_mapping       = edma_tc_mapping,
        .queue_priority_mapping = edma_priority_mapping,
+       .default_queue          = EVENTQ_1,
 };
 
 static struct edma_soc_info *tnetv107x_edma_info[EDMA_MAX_CC] = {
index a3a94e9c93784b10a6d98c3b379a680def7641e2..68fb181624594ed37c53a646642c0f8422e7139d 100644 (file)
@@ -591,6 +591,7 @@ static struct edma_soc_info edma_cc0_info = {
        .n_cc                   = 1,
        .queue_tc_mapping       = queue_tc_mapping,
        .queue_priority_mapping = queue_priority_mapping,
+       .default_queue          = EVENTQ_1,
 };
 
 static struct edma_soc_info *dm355_edma_info[EDMA_MAX_CC] = {
index 4c82c2716293a6e750f242c128fb14e66c2ce636..555ff5bdb2207e95c7eb083b2a6794a9c6d866a1 100644 (file)
@@ -514,6 +514,7 @@ static struct edma_soc_info edma_cc0_info = {
        .n_cc                   = 1,
        .queue_tc_mapping       = queue_tc_mapping,
        .queue_priority_mapping = queue_priority_mapping,
+       .default_queue          = EVENTQ_1,
 };
 
 static struct edma_soc_info *dm644x_edma_info[EDMA_MAX_CC] = {
index 1802e711a2b8f7218131613365f19e4361ff04e2..b0c350a02484e808816825cafc8baa6ec31ecae1 100644 (file)
@@ -555,6 +555,7 @@ static struct edma_soc_info edma_cc0_info = {
        .n_cc                   = 1,
        .queue_tc_mapping       = dm646x_queue_tc_mapping,
        .queue_priority_mapping = dm646x_queue_priority_mapping,
+       .default_queue          = EVENTQ_1,
 };
 
 static struct edma_soc_info *dm646x_edma_info[EDMA_MAX_CC] = {
index 6b9669869c4680d7eedc992ec98078c01b5f5131..6ba4191d6570c76f34077f15cd85bb91a5cc0550 100644 (file)
@@ -1450,8 +1450,6 @@ static int __init edma_probe(struct platform_device *pdev)
                                                        EDMA_MAX_CC);
 
                edma_cc[j]->default_queue = info[j]->default_queue;
-               if (!edma_cc[j]->default_queue)
-                       edma_cc[j]->default_queue = EVENTQ_1;
 
                dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
                        edmacc_regs_base[j]);