]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
ARM: dts: imx: add cooling-cells for cpufreq cooling device
authorAnson Huang <Anson.Huang@nxp.com>
Fri, 8 Jun 2018 09:06:40 +0000 (11:06 +0200)
committerShawn Guo <shawnguo@kernel.org>
Thu, 28 Jun 2018 00:59:09 +0000 (08:59 +0800)
Add #cooling-cells for i.MX6/7 SoCs for cpufreq cooling device usage.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Bastian Stender <bst@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/imx6dl.dtsi
arch/arm/boot/dts/imx6q.dtsi
arch/arm/boot/dts/imx6sl.dtsi
arch/arm/boot/dts/imx6sx.dtsi
arch/arm/boot/dts/imx6ul.dtsi
arch/arm/boot/dts/imx7d.dtsi

index b384913c34ddaf4ed6df751b083abd35d15b454d..a1acd4ddcb1a4f903fbdad591c4cdb0713a5b22a 100644 (file)
@@ -33,6 +33,7 @@ cpu@0 {
                                396000  1175000
                        >;
                        clock-latency = <61036>; /* two CLK32 periods */
+                       #cooling-cells = <2>;
                        clocks = <&clks IMX6QDL_CLK_ARM>,
                                 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
                                 <&clks IMX6QDL_CLK_STEP>,
index 70483ce72ba6cf648809acb7f24be3af11817674..894401c5db0922cbb5ffdbc4ef573da9b5eb204a 100644 (file)
@@ -38,6 +38,7 @@ cpu0: cpu@0 {
                                396000  1175000
                        >;
                        clock-latency = <61036>; /* two CLK32 periods */
+                       #cooling-cells = <2>;
                        clocks = <&clks IMX6QDL_CLK_ARM>,
                                 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
                                 <&clks IMX6QDL_CLK_STEP>,
index 994e48dc1df0a01e1be33c2bc8750e453b83ddb4..81f48116c5b1283907f93e635ec50d5375a3506b 100644 (file)
@@ -60,6 +60,7 @@ cpu@0 {
                                396000          1175000
                        >;
                        clock-latency = <61036>; /* two CLK32 periods */
+                       #cooling-cells = <2>;
                        clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
                                        <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
                                        <&clks IMX6SL_CLK_PLL1_SYS>;
index d8b94f47498b67051ade669f23d2796a0b1e7433..7130ab8a75188e115ace42f19fed4bbf58b88630 100644 (file)
@@ -79,6 +79,7 @@ cpu0: cpu@0 {
                                198000      1175000
                        >;
                        clock-latency = <61036>; /* two CLK32 periods */
+                       #cooling-cells = <2>;
                        clocks = <&clks IMX6SX_CLK_ARM>,
                                 <&clks IMX6SX_CLK_PLL2_PFD2>,
                                 <&clks IMX6SX_CLK_STEP>,
index 47a3453a4211fe2bebe5bb72c0d42ae370c66b43..36572b62a4afa85cbd624210501846f344906884 100644 (file)
@@ -62,6 +62,7 @@ cpu0: cpu@0 {
                        device_type = "cpu";
                        reg = <0>;
                        clock-latency = <61036>; /* two CLK32 periods */
+                       #cooling-cells = <2>;
                        operating-points = <
                                /* kHz  uV */
                                696000  1275000
index 8d3d123d0a5c679c5fecd7ca756c9cd4d76ef727..7cbc2ffa4b3a80affe055aecf6f744f4a61a9d00 100644 (file)
@@ -11,6 +11,7 @@ cpus {
                cpu0: cpu@0 {
                        clock-frequency = <996000000>;
                        operating-points-v2 = <&cpu0_opp_table>;
+                       #cooling-cells = <2>;
                };
 
                cpu1: cpu@1 {