drm/exynos: mixer: enable NV12MT support for the video plane

The video processor supports a tiled version of the NV12 format,
known as NV12MT in V4L2 terms. The support was removed in commit
083500baefd5f4c215a5a93aef2492c1aa775828 due to not being a real
pixel format, but rather NV12 with a special memory layout.

With the introduction of FB modifiers, we can now properly support
this format again.

Tested with a hacked up modetest from libdrm's test suite on
an ODROID-X2 (Exynos4412).

Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: Inki Dae <inki.dae@samsung.com>

diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index d53435b68ae6ea88923446ebcbf0893b9962169b..cf131c2aa23e431f13a44fe1985bad58c32da250 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -91,6 +91,7 @@ struct exynos_drm_plane {
 #define EXYNOS_DRM_PLANE_CAP_DOUBLE    (1 << 0)
 #define EXYNOS_DRM_PLANE_CAP_SCALE     (1 << 1)
 #define EXYNOS_DRM_PLANE_CAP_ZPOS      (1 << 2)
+#define EXYNOS_DRM_PLANE_CAP_TILE      (1 << 3)
 
 /*
  * Exynos DRM plane configuration structure.

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.c b/drivers/gpu/drm/exynos/exynos_drm_fb.c
index 6592f50d460a6843e39222cf4f39152d6d34f190..8208df56a88f7f9fcc6b82ff6b1fc1f569671e9e 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_drm_fb.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fb.c
@@ -225,4 +225,6 @@ void exynos_drm_mode_config_init(struct drm_device *dev)
 
        dev->mode_config.funcs = &exynos_drm_mode_config_funcs;
        dev->mode_config.helper_private = &exynos_drm_mode_config_helpers;
+
+       dev->mode_config.allow_fb_modifiers = true;
 }

diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c
index 8de74009dee4f439bbf2306c254c95723a1ac1fd..d2a90dae5c71085c6ac919bc709c8dd378e39863 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_drm_plane.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c
@@ -178,6 +178,29 @@ static struct drm_plane_funcs exynos_plane_funcs = {
        .atomic_destroy_state = exynos_drm_plane_destroy_state,
 };
 
+static int
+exynos_drm_plane_check_format(const struct exynos_drm_plane_config *config,
+                             struct exynos_drm_plane_state *state)
+{
+       struct drm_framebuffer *fb = state->base.fb;
+
+       switch (fb->modifier) {
+       case DRM_FORMAT_MOD_SAMSUNG_64_32_TILE:
+               if (!(config->capabilities & EXYNOS_DRM_PLANE_CAP_TILE))
+                       return -ENOTSUPP;
+               break;
+
+       case DRM_FORMAT_MOD_LINEAR:
+               break;
+
+       default:
+               DRM_ERROR("unsupported pixel format modifier");
+               return -ENOTSUPP;
+       }
+
+       return 0;
+}
+
 static int
 exynos_drm_plane_check_size(const struct exynos_drm_plane_config *config,
                            struct exynos_drm_plane_state *state)
@@ -222,6 +245,10 @@ static int exynos_plane_atomic_check(struct drm_plane *plane,
        /* translate state into exynos_state */
        exynos_plane_mode_set(exynos_state);
 
+       ret = exynos_drm_plane_check_format(exynos_plane->config, exynos_state);
+       if (ret)
+               return ret;
+
        ret = exynos_drm_plane_check_size(exynos_plane->config, exynos_state);
        return ret;
 }

diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index cbd949a989f9f04b891421906f49ec275071b9b6..f9a06b8007c51f180c6caa94717483537f8b4d58 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -148,7 +148,8 @@ static const struct exynos_drm_plane_config plane_configs[MIXER_WIN_NR] = {
                .pixel_formats = vp_formats,
                .num_pixel_formats = ARRAY_SIZE(vp_formats),
                .capabilities = EXYNOS_DRM_PLANE_CAP_SCALE |
-                               EXYNOS_DRM_PLANE_CAP_ZPOS,
+                               EXYNOS_DRM_PLANE_CAP_ZPOS |
+                               EXYNOS_DRM_PLANE_CAP_TILE,
        },
 };
 
@@ -500,6 +501,9 @@ static void vp_video_buffer(struct mixer_context *ctx,
                return;
        }
 
+       if (fb->modifier == DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
+               tiled_mode = true;
+
        luma_addr[0] = exynos_drm_fb_dma_addr(fb, 0);
        chroma_addr[0] = exynos_drm_fb_dma_addr(fb, 1);