arm64: dts: meson-g12: add Everything-Else power domain controller

Replace the VPU-centric power domain controller by the generic system-wide
Everything-Else power domain controller and setup the right power-domains
properties on the VPU, Ethernet & USB nodes.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
[khilman: minor subject edit: add dts]
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
index d09c7a5cccb407d9326f40886b8c379cc7fc7317..ea1411b4a2873cfa9dba432ac4e55ef41ae9f0a4 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
@@ -1406,6 +1406,53 @@ clkc: clock-controller {
                                                clocks = <&xtal>;
                                                clock-names = "xtal";
                                        };
+
+                                       pwrc: power-controller {
+                                               compatible = "amlogic,meson-g12a-pwrc";
+                                               #power-domain-cells = <1>;
+                                               amlogic,ao-sysctrl = <&rti>;
+                                               resets = <&reset RESET_VIU>,
+                                                        <&reset RESET_VENC>,
+                                                        <&reset RESET_VCBUS>,
+                                                        <&reset RESET_BT656>,
+                                                        <&reset RESET_RDMA>,
+                                                        <&reset RESET_VENCI>,
+                                                        <&reset RESET_VENCP>,
+                                                        <&reset RESET_VDAC>,
+                                                        <&reset RESET_VDI6>,
+                                                        <&reset RESET_VENCL>,
+                                                        <&reset RESET_VID_LOCK>;
+                                               reset-names = "viu", "venc", "vcbus", "bt656",
+                                                             "rdma", "venci", "vencp", "vdac",
+                                                             "vdi6", "vencl", "vid_lock";
+                                               clocks = <&clkc CLKID_VPU>,
+                                                        <&clkc CLKID_VAPB>;
+                                               clock-names = "vpu", "vapb";
+                                               /*
+                                                * VPU clocking is provided by two identical clock paths
+                                                * VPU_0 and VPU_1 muxed to a single clock by a glitch
+                                                * free mux to safely change frequency while running.
+                                                * Same for VAPB but with a final gate after the glitch free mux.
+                                                */
+                                               assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
+                                                                 <&clkc CLKID_VPU_0>,
+                                                                 <&clkc CLKID_VPU>, /* Glitch free mux */
+                                                                 <&clkc CLKID_VAPB_0_SEL>,
+                                                                 <&clkc CLKID_VAPB_0>,
+                                                                 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
+                                               assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+                                                                        <0>, /* Do Nothing */
+                                                                        <&clkc CLKID_VPU_0>,
+                                                                        <&clkc CLKID_FCLK_DIV4>,
+                                                                        <0>, /* Do Nothing */
+                                                                        <&clkc CLKID_VAPB_0>;
+                                               assigned-clock-rates = <0>, /* Do Nothing */
+                                                                      <666666666>,
+                                                                      <0>, /* Do Nothing */
+                                                                      <0>, /* Do Nothing */
+                                                                      <250000000>,
+                                                                      <0>; /* Do Nothing */
+                                       };
                                };
                        };
 
@@ -1753,50 +1800,6 @@ clkc_AO: clock-controller {
                                        clock-names = "xtal", "mpeg-clk";
                                };
 
-                               pwrc_vpu: power-controller-vpu {
-                                       compatible = "amlogic,meson-g12a-pwrc-vpu";
-                                       #power-domain-cells = <0>;
-                                       amlogic,hhi-sysctrl = <&hhi>;
-                                       resets = <&reset RESET_VIU>,
-                                                <&reset RESET_VENC>,
-                                                <&reset RESET_VCBUS>,
-                                                <&reset RESET_BT656>,
-                                                <&reset RESET_RDMA>,
-                                                <&reset RESET_VENCI>,
-                                                <&reset RESET_VENCP>,
-                                                <&reset RESET_VDAC>,
-                                                <&reset RESET_VDI6>,
-                                                <&reset RESET_VENCL>,
-                                                <&reset RESET_VID_LOCK>;
-                                       clocks = <&clkc CLKID_VPU>,
-                                                <&clkc CLKID_VAPB>;
-                                       clock-names = "vpu", "vapb";
-                                       /*
-                                        * VPU clocking is provided by two identical clock paths
-                                        * VPU_0 and VPU_1 muxed to a single clock by a glitch
-                                        * free mux to safely change frequency while running.
-                                        * Same for VAPB but with a final gate after the glitch free mux.
-                                        */
-                                       assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
-                                                         <&clkc CLKID_VPU_0>,
-                                                         <&clkc CLKID_VPU>, /* Glitch free mux */
-                                                         <&clkc CLKID_VAPB_0_SEL>,
-                                                         <&clkc CLKID_VAPB_0>,
-                                                         <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
-                                       assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
-                                                                <0>, /* Do Nothing */
-                                                                <&clkc CLKID_VPU_0>,
-                                                                <&clkc CLKID_FCLK_DIV4>,
-                                                                <0>, /* Do Nothing */
-                                                                <&clkc CLKID_VAPB_0>;
-                                       assigned-clock-rates = <0>, /* Do Nothing */
-                                                              <666666666>,
-                                                              <0>, /* Do Nothing */
-                                                              <0>, /* Do Nothing */
-                                                              <250000000>,
-                                                              <0>; /* Do Nothing */
-                               };
-
                                ao_pinctrl: pinctrl@14 {
                                        compatible = "amlogic,meson-g12a-aobus-pinctrl";
                                        #address-cells = <2>;
@@ -2149,7 +2152,6 @@ vpu: vpu@ff900000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        amlogic,canvas = <&canvas>;
-                       power-domains = <&pwrc_vpu>;
 
                        /* CVBS VDAC output port */
                        cvbs_vdac_port: port@0 {

diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index 733a9d46fc4bd3f848e7604458c31bf6ed109108..eb5d177d7a999311e21ff1cc8ceb8350908c8611 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -4,6 +4,7 @@
  */
 
 #include "meson-g12-common.dtsi"
+#include <dt-bindings/power/meson-g12a-power.h>
 
 / {
        compatible = "amlogic,g12a";
@@ -110,6 +111,14 @@ opp-1800000000 {
        };
 };
 
+&ethmac {
+       power-domains = <&pwrc PWRC_G12A_ETH_ID>;
+};
+
+&vpu {
+       power-domains = <&pwrc PWRC_G12A_VPU_ID>;
+};
+
 &sd_emmc_a {
        amlogic,dram-access-quirk;
 };

diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
index d5edbc1a19911a1d724b804e7be33a731ecb7142..5628ccd54531ac28e11d5eb3683344c6cef25991 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
@@ -5,6 +5,7 @@
  */
 
 #include "meson-g12-common.dtsi"
+#include <dt-bindings/power/meson-g12a-power.h>
 
 / {
        compatible = "amlogic,g12b";
@@ -101,6 +102,14 @@ &clkc {
        compatible = "amlogic,g12b-clkc";
 };
 
+&ethmac {
+       power-domains = <&pwrc PWRC_G12A_ETH_ID>;
+};
+
+&vpu {
+       power-domains = <&pwrc PWRC_G12A_VPU_ID>;
+};
+
 &sd_emmc_a {
        amlogic,dram-access-quirk;
 };

diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
index e902d4f9165fc1d9fa4ef04d15c761d2ea355aad..2322836aba65409b20af6bba71f4296a515a1df2 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
@@ -5,6 +5,7 @@
  */
 
 #include "meson-g12-common.dtsi"
+#include <dt-bindings/power/meson-sm1-power.h>
 
 / {
        compatible = "amlogic,sm1";
@@ -59,10 +60,19 @@ &clk_msr {
        compatible = "amlogic,meson-sm1-clk-measure";
 };
 
-&pwrc_vpu {
-       status = "disabled";
+
+&ethmac {
+       power-domains = <&pwrc PWRC_SM1_ETH_ID>;
+};
+
+&pwrc {
+       compatible = "amlogic,meson-sm1-pwrc";
 };
 
 &vpu {
-       status = "disabled";
+       power-domains = <&pwrc PWRC_SM1_VPU_ID>;
+};
+
+&usb {
+       power-domains = <&pwrc PWRC_SM1_USB_ID>;
 };