clk: imx6q: Do not reparent uninitialized IMX6QDL_CLK_PERIPH2 clock

The clock is registered later than these two re-parentings.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index 077276b0933873041fb538ef36666c9e4f70d2cd..d90d54bf78fefddf95e2ef39a8d903e48e3fc686 100644 (file)
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -280,12 +280,6 @@ static void mmdc_ch1_disable(void __iomem *ccm_base)
        clk_set_parent(clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL],
                       clk[IMX6QDL_CLK_PLL3_USB_OTG]);
 
-       /*
-        * Handshake with mmdc_ch1 module must be masked when changing
-        * periph2_clk_sel.
-        */
-       clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_CLK2]);
-
        /* Disable pll3_sw_clk by selecting the bypass clock source */
        reg = readl_relaxed(ccm_base + CCM_CCSR);
        reg |= CCSR_PLL3_SW_CLK_SEL;
@@ -300,8 +294,6 @@ static void mmdc_ch1_reenable(void __iomem *ccm_base)
        reg = readl_relaxed(ccm_base + CCM_CCSR);
        reg &= ~CCSR_PLL3_SW_CLK_SEL;
        writel_relaxed(reg, ccm_base + CCM_CCSR);
-
-       clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_PRE]);
 }
 
 /*